Effective parallel processing techniques for the generation of test data for a logic built-in self test system

2002 ◽  
Author(s):  
P. Chang ◽  
B. Keller ◽  
S. Paliwal
Keyword(s):  
Parallel Processing ◽  
Test Data ◽  
Test System ◽  
Self Test ◽  
Built In Self Test ◽  
Processing Techniques

A 76–84-GHz 16-Element Phased-Array Receiver With a Chip-Level Built-In Self-Test System

2013 ◽  
Vol 61 (8) ◽  
pp. 3083-3098 ◽  
Author(s):  
Sang Young Kim ◽  
Ozgur Inac ◽  
Choul-Young Kim ◽  
Donghyup Shin ◽  
Gabriel M. Rebeiz
Keyword(s):  
Phased Array ◽  
Test System ◽  
Self Test ◽  
Built In Self Test ◽  
Array Receiver

scholarly journals A Built-in Self-Test System for External DRAM

2020 ◽  
pp. 80-87
Author(s):  
Gor Abgaryan
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Efficiency ◽  
Random Access ◽  
Test System ◽  
Mass Storage ◽  
Access Memory ◽  
Yield And Quality ◽  
Self Test ◽  
Built In Self Test

In the fast-growing Integrated Circuits (IC) industry, memory is one of the few keys to have systems with improved and fast performance. Only one transistor and a capacitor are required for Dynamic Random-Access Memory (DRAM) bit. It is widely used for mass storage. Although the high-efficiency tests are performed to provide the reliability of the memories, maintaining acceptable yield and quality is still the most critical task. To perform a high-speed effective test of DRAM memories, a built-in self-test (BIST) mechanism is proposed.

Design of an Oscillation-Based BIST System for Active Analog Integrated Filters in 0.18 µm CMOS

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 813 ◽  
Author(s):  
Leonid Kladovščikov ◽  
Marijan Jurgo ◽  
Romualdas Navickas
Keyword(s):  
Cmos Technology ◽  
Test System ◽  
Oxide Semiconductor ◽  
Analog Filters ◽  
Detection Range ◽  
Active Analog ◽  
Parametric Faults ◽  
Self Test ◽  
Built In Self Test ◽  
Catastrophic Faults

In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.

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