scholarly journals Fault-tolerant ASIC: Design and implementation

2013 ◽  
Vol 26 (3) ◽  
pp. 175-186 ◽  
Author(s):  
Z. Stamenkovic ◽  
V. Petrovic ◽  
G. Schoof
Keyword(s):  
Fault Tolerant ◽  
Logic Synthesis ◽  
Design Flow ◽  
Single Event ◽  
Asic Design ◽  
Single Event Upsets ◽  
Design And Implementation ◽  
Standard Design ◽  
Extra Step ◽  
Definition Of

The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

Modeling of single event upsets for fault-tolerant system validation

1993 ◽  
Author(s):  
Hungse Cha ◽  
Gwan Choi ◽  
Janak Patel ◽  
Ravishankar Iyer
Keyword(s):  
Fault Tolerant ◽  
Single Event ◽  
Fault Tolerant System ◽  
Single Event Upsets ◽  
System Validation

SYSTEM LEVEL SINGLE EVENT UPSET MITIGATION STRATEGIES

2004 ◽  
Vol 14 (02) ◽  
pp. 341-352 ◽  
Author(s):  
W. F. HEIDERGOTT
Keyword(s):  
Systems Engineering ◽  
Fault Tolerant ◽  
Systems Design ◽  
Essential Elements ◽  
Mitigation Strategies ◽  
System Level ◽  
Single Event ◽  
Single Event Upsets ◽  
Fault Masking ◽  
And Performance

Use of a systems engineering process and the application of techniques and methods of fault tolerant systems are applicable to the development of a mitigation strategy for Single Event Upsets (SEU). Specific methods of fault avoidance, fault masking, detection, containment, and recovery techniques are important elements in the mitigation of single event upsets. Fault avoidance through the use of SEU hardened technology, fault masking using coding and redundancy provisions, and solutions applied at the subsystem and system level are available to the system developer. Validation and verification of SEU mitigation and performance of fault tolerance provisions are essential elements of systems design for operation in energetic particle environments.

scholarly journals Low power synthesis for asynchronous FIFO using unified power format (UPF)

2018 ◽  
Vol 7 (2.8) ◽  
pp. 7
Author(s):  
Avinash Yadlapati ◽  
K Hari Kishore
Keyword(s):  
Low Power ◽  
Logic Synthesis ◽  
Reducing Power ◽  
Low Power Design ◽  
Design Flow ◽  
Functional Verification ◽  
Design For Test ◽  
Asic Design ◽  
The Common ◽  
Low Power Synthesis

Low power Design is the challenge for the current SoC Designers. With the growing complexity of the chips and the shrinking technology, power consumption in ASIC’s has become a major challenge for the ASIC Engineer. The low power challenge is at every level of the ASIC Design flow. The low power techniques are applies at the Micro architecture level, RTL Design Level, Functional Verification level, Logic Synthesis level, Design for Test level, and Physical Design level. Nowadays, with the complexity gradually increasing at the SoC level, some of the EDA companies like Synopsys and Cadence are integrating the low power techniques in the tool itself. For instance, the two most commonly used low power flows are Unified Power Format (UPF) and Common Power Format (CPF). The Unified power format is from Synopsys flow while the Common Power format is from Cadence flow. In this paper, the emphasis is on reducing power by taking an Asynchronous FIFO with two separate clocks and applying the Unified power format flow in it. This paper presents the results of the research reported by the Synopsys Design Compiler before applying the UPF flow and after applying the UPF flow.

scholarly journals Virtual Loom: a tool for the interactive 3D representation of historical fabrics

2021 ◽  
Author(s):  
Cristina Portalés ◽  
Manolo Pérez ◽  
Pablo Casanova-Salas ◽  
Jesús Gimeno
Keyword(s):  
Art History ◽  
3D Modelling ◽  
Current Version ◽  
Close Collaboration ◽  
Design And Implementation ◽  
Different Types ◽  
Interactive 3D ◽  
Silk Fabrics ◽  
Definition Of ◽  
3D Representations

Abstract3D modelling of man-made objects is widely used in the cultural heritage sector, among others. It is relevant for its documentation, dissemination and preservation. Related to historical fabrics, weaves and weaving techniques are still mostly represented in forms of 2D graphics and textual descriptions. However, complex geometries are difficult to represent in such forms, hindering the way this legacy is transmitted to new generations. In this paper, we present the design and implementation of SILKNOW’s Virtual Loom, an interactive tool aimed to document, preserve and represent in interactive 3D forms historical weaves and weaving techniques of silk fabrics, dating from the 15th to the 19th centuries. To that end, our tool only requires an image of a historical fabric. Departing from this image, the tool automatically subtracts the design, and allows the user to apply different weaves and weaving techniques. In its current version, the tool embeds five traditional weaving techniques, 39 weaves and six types of yarns, which have been defined thanks to close collaboration of experts in computer graphics, art history and historical fabrics. Additionally, users can change the color of yarns and produce different 3D representations for a given fabric, which are interactive in real time. In this paper, we bring the details of the design and implementation of this tool, focusing on the input data, the strategy to process images, the 3D modelling of yarns, the definition of weaves and weaving techniques and the graphical user interface. In the results section, we show some examples of image analysis in order to subtract the design of historical fabrics, and then we provide 3D representations for all the considered weaving techniques, combining different types of yarns.

Neutron and proton-induced single event upsets in advanced commercial fully depleted SOI SRAMs

2005 ◽  
Vol 52 (6) ◽  
pp. 2319-2325 ◽  
Author(s):  
J. Baggio ◽  
V. Ferlet-Cavrois ◽  
D. Lambert ◽  
P. Paillet ◽  
F. Wrobel ◽  
...  
Keyword(s):  
Single Event ◽  
Fully Depleted ◽  
Single Event Upsets
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