Modeling of single event upsets for fault-tolerant system validation

1993 ◽  
Author(s):  
Hungse Cha ◽  
Gwan Choi ◽  
Janak Patel ◽  
Ravishankar Iyer
Keyword(s):  
Fault Tolerant ◽  
Single Event ◽  
Fault Tolerant System ◽  
Single Event Upsets ◽  
System Validation

scholarly journals Fault-tolerant ASIC: Design and implementation

2013 ◽  
Vol 26 (3) ◽  
pp. 175-186 ◽  
Author(s):  
Z. Stamenkovic ◽  
V. Petrovic ◽  
G. Schoof
Keyword(s):  
Fault Tolerant ◽  
Logic Synthesis ◽  
Design Flow ◽  
Single Event ◽  
Asic Design ◽  
Single Event Upsets ◽  
Design And Implementation ◽  
Standard Design ◽  
Extra Step ◽  
Definition Of

The paper presents fault-tolerant CMOS ASICs which are immune to the single event upsets (SEU), the single event transients (SET), and the single event latchup (SEL). Triple and double modular redundant (TMR and DMR) circuits and SEL protection switches (SPS) make the base for a modified fault-tolerant ASIC design flow. The proposed design flow requires the standard design automation tools and a few additional steps during logic synthesis and layout generation. An extra step is necessary to generate the redundant design net-list including voters. Other two extra steps (definition of the redundant power domains and placement of the SPS) have to be performed in the layout phase. The concept has been proven by design and implementation of the two digital circuits: shift-register and synchronous counter.

SYSTEM LEVEL SINGLE EVENT UPSET MITIGATION STRATEGIES

2004 ◽  
Vol 14 (02) ◽  
pp. 341-352 ◽  
Author(s):  
W. F. HEIDERGOTT
Keyword(s):  
Systems Engineering ◽  
Fault Tolerant ◽  
Systems Design ◽  
Essential Elements ◽  
Mitigation Strategies ◽  
System Level ◽  
Single Event ◽  
Single Event Upsets ◽  
Fault Masking ◽  
And Performance

Use of a systems engineering process and the application of techniques and methods of fault tolerant systems are applicable to the development of a mitigation strategy for Single Event Upsets (SEU). Specific methods of fault avoidance, fault masking, detection, containment, and recovery techniques are important elements in the mitigation of single event upsets. Fault avoidance through the use of SEU hardened technology, fault masking using coding and redundancy provisions, and solutions applied at the subsystem and system level are available to the system developer. Validation and verification of SEU mitigation and performance of fault tolerance provisions are essential elements of systems design for operation in energetic particle environments.

Neutron and proton-induced single event upsets in advanced commercial fully depleted SOI SRAMs

2005 ◽  
Vol 52 (6) ◽  
pp. 2319-2325 ◽  
Author(s):  
J. Baggio ◽  
V. Ferlet-Cavrois ◽  
D. Lambert ◽  
P. Paillet ◽  
F. Wrobel ◽  
...  
Keyword(s):  
Single Event ◽  
Fully Depleted ◽  
Single Event Upsets

Fault-Tolerant Strategy for Real-Time System Based on Evolvable Hardware

2017 ◽  
Vol 26 (07) ◽  
pp. 1750111 ◽  
Author(s):  
Jie Wang ◽  
Jiwei Liu
Keyword(s):  
Real Time ◽  
Recovery Time ◽  
Fault Tolerant ◽  
Fault Tree Analysis ◽  
Repair Process ◽  
Evolvable Hardware ◽  
Target System ◽  
Time System ◽  
Real Time System ◽  
Fault Tolerant System

The evolvable hardware (EHW) is widely used in the design of fault-tolerant system. Fault-tolerant system is really a real-time system, and the recovery time is necessary in fault detection and recovery. However, when applying EHW, real-time characteristic is usually ignored. In this paper, a fault-tolerant strategy based on EHW is proposed. The recovery time, predicted by the fault tree analysis (FTA), is considered as a constraint condition. A configuration library is set up in the design phase to accelerate the repair process of the anticipated faults. An evolvable algorithm (EA) based on similarity is applied to evolve the repair circuit for the unanticipated faults. When the library reaches the upper, the target system is reconfigured by the EA-repair technology. Extensive experiments are conducted to show that our method can improve the fault-tolerance of the system while satisfying the real-time requirement on FPGA platform. In a long run system, our method can keep a higher fault recovery rate.

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