With the increasing electronics demand on complexity and functionality, low temperature cofired ceramic (LTCC) shows its advantages for cost efficiency under high volume, multilayer high packaging density, and compatibility of passive components integration. However, compared with thin film technology, the minimum thick film line width and spacing on LTCC is 4mil, which limits the packaging of fine pitch devices. In this study, one of DuPont™ photoimageable thick film gold (Au) conductors has been selected to fabricate on DuPont 951PX substrate, with the patterns as small as 1mil. Surface insulation resistance (SIR) and serpentine resistance patterns with a series of line width and spacing was printed and post fired on LTCC to investigate the capabilities and limits of the feature size. Feature dimensions were measured to compare with the design value. Metal adhesion and stud bump patterns are also included in the test substrate. After initial testing, the substrates are undergoing 300°C aging. Post aging resistance measurement, metallization adhesion pull test and Au stud bump shear test are carried out to evaluate its high temperature behaviors.
An analysis of the pull strength behaviors of fine-pitch, flip chip solder interconnections using a Au-Pt-Pd thick film conductor on Low-Temperature, Co-fired Ceramic (LTCC) substrates.