Low Temperature and Ultra Fine Pitch Joints Using Non-Conductive Adhesive for Flip Chip Technology

2006 ◽  
Author(s):  
Soo Yeol Kim ◽  
Tae-Sung Oh ◽  
Won Jong Lee ◽  
Young-Ho Kim
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Conductive Adhesive ◽  
Chip Technology ◽  
Fine Pitch

Fine pitch low-cost bumping for flip chip technology

2003 ◽  
Author(s):  
Szu-Wei Lu ◽  
Ruoh-Huey Uang ◽  
Kuo-Chuan Chen ◽  
Hsu-Tien Hu ◽  
Ling-Chen Kung ◽  
...  
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Chip Technology ◽  
Fine Pitch

Corrections to "Ultra-fine pitch stencil printing for a low cost and low temperature flip-chip assembly process"

2007 ◽  
Vol 30 (2) ◽  
pp. 359-359
Author(s):  
Robert W. Kay ◽  
Stoyan Stoyanov ◽  
Greg P. Glinski ◽  
Chris Bailey ◽  
Marc P. Y. Desmulliez
Keyword(s):  
Low Temperature ◽  
Flip Chip ◽  
Low Cost ◽  
Assembly Process ◽  
Stencil Printing ◽  
Fine Pitch ◽  
Flip Chip Assembly

Process Modeling and Thermal/Mechanical Behavior of ACA/ACF Type Flip-Chip Packages

2001 ◽  
Vol 123 (4) ◽  
pp. 331-337 ◽  
Author(s):  
K. N. Chiang ◽  
C. W. Chang ◽  
C. T. Lin
Keyword(s):  
Tensile Stress ◽  
Process Modeling ◽  
Flip Chip ◽  
Thermal Loading ◽  
Conductive Adhesive ◽  
Adhesive Film ◽  
Anisotropic Conductive Adhesive ◽  
Fine Pitch ◽  
Assembly Technology ◽  
Conductive Particles

Development of flip-chip-on-glass (FCOG) assembly technology using anisotropic conductive adhesive/film (ACA/ACF) is currently underway to achieve fine pitch interconnections between driver IC and flat panel display. Conductive adhesives are characterized by fine-pitch capability and more environment compatibility. Anisotropic conductive adhesive/film (ACA/ACF) is composed of an adhesive resin and conductive particles, such as metallic or metal-coated polymer particles. In contrast to a solder type flip chip interconnection, the electric current passing through conductive particles becomes the dominant conduction paths. The interconnection between the particles and the conductive surfaces is constructed by the elastic/plastic deformation of conductive particles with contact pressure, which is maintained by tensile stress in the adhesive. Although loss of electric contact can occur when the adhesive expands or swells in the Z- axis direction, delamination and cracking can occur in the adhesive layer while the tensile stress is excessive. In addition to performing processing simulations as well as reliability modeling, this research investigates the contact force that is developed and relaxed within the interconnection during the process sequence by using nonlinear finite element simulations. Environmental effects, such as high temperature and thermal loading, are also discussed. Moreover, a parametric study is performed for process design. To improve performance and reliability, variables such as ACF materials, proper processing conditions are discussed as well. Furthermore, this study presents a novel method called equivalent spring method, capable of significantly reducing the analysis CPU time and make process modeling and contact analysis of the 3D ACA/ACF process possible.

Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology

1998 ◽  
Vol 21 (1) ◽  
pp. 41-50 ◽  
Author(s):  
J. Kloeser ◽  
K. Heinricht ◽  
K. Kutzner ◽  
E. Jung ◽  
A. Ostmann ◽  
...  
Keyword(s):  
Flip Chip ◽  
Lead Free ◽  
Stencil Printing ◽  
Chip Technology ◽  
Fine Pitch ◽  
Lead Free Solders

Processing and Reliability Assessment of Silicon Based, Integrated Ultra High Density Substrates

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002272-002313
Author(s):  
Brian J. Lewis ◽  
D. F. Baldwin ◽  
P. N. Houston ◽  
B. Smith ◽  
P. Kwok ◽  
...  
Keyword(s):  
Flip Chip ◽  
Reliability Assessment ◽  
High Density ◽  
Chip Technology ◽  
Fine Pitch ◽  
Characterization Study ◽  
Alternative Materials ◽  
Full Analysis ◽  
Silicon Vias ◽  
Silicon Based

High density interconnect (HDI) advances in substrate technology have allowed considerable improvements in processing more complex, compact devices. Chip Scale Packaging (CSP) and multi-chip modules (MCM) have continued to decrease in size and increase in functionality, moving closer to be more like flip chip technology. Improvements in wafer structuring allow for tremendous possibilities for device functionality; however a limit does exists on what traditional substrate fabrication methods will allow. A push in developing through silicon vias (TSVs) and use of alternative materials, other than organic or flex, are needed to enable new packaging technology developments. As needed, an alternative substrate has been developed that uses Silicon-based technology, photo-defined vias and the capability of semiconductor level routing density. It also includes the possibility to open cavities in the substrate to embed integrated die. This technology has opened up many possibilities for fabricating Ultra high density substrates from a US-based supplier that enables the use of integrated die, surface mount processing and fine pitch, multi-die placements. The following paper details the processing and reliability capabilities of this substrate technology. A comprehensive characterization study was conducted to evaluate the processing of units containing ultra-small SMT devices, intermixed with fine pitch, flip chip die. The units were also processed with traditional BGA balling, making them compatible with level 2, PCB level processes. Data will be shown with the results of the assembly analysis and subsequent reliability assessment of these units, showing a robust performance with thermal shock, uHAST and MSL level testing. A full analysis of the substrates structure will also be shown. The paper will show this technology's possibilities as a next generation substrate alternative.

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