Optimization of the Au Stud Bump Number for the Flip-Chip Packaged InGaN LEDs

Au stud bump can provide a good heat spreading path for the flip-chip LED due to its high thermal conductivity (300 W/mK) . In this paper, we compared four flip-chip LED devices with four different numbers of Au stud bumps. The thermal imaging analysis indicates that the heat dissipation is proportional to the number of Au stud bump. However, when the number of Au stud bumps was larger than 24, the heat dissipation performance will become deteriorated due to the poor bonding between grain and substrate. Therefore, the number of Au stud bumps was optimized to be 20 to 24, which can be employed to develop flip-chip LEDs with optimum electrical and optical performance.

Recent Progress in Thin Film Multichip Packaging for High Temperature Digital Electronics

A thin film material and process technology is being developed and evaluated for high temperature (300°C) digital multichip modules for use in geothermal well instrumentation. The substrate technology selected is AlN to minimize the difference in the coefficient of thermal expansion between the substrate and the SiC digital die. A thin film/plated Ti/Ti:W/Au metallization is used with a plasma enhanced chemical vapor deposited Si3N4 to create multilayer interconnections. Active components are assembled to the interconnect substrate using Au stud bump thermocompression bonding. The Au stud bump maintains a monometallic interface between the substrate Au pad surface and the Au pads on the SiC die. A digital circuit has been built and successfully tested as an initial demonstration.

Investigation of Photo-Imageable Thick Film Metallization on Low Temperature Cofired Ceramics (LTCC) for Improved Packaging Density

With the increasing electronics demand on complexity and functionality, low temperature cofired ceramic (LTCC) shows its advantages for cost efficiency under high volume, multilayer high packaging density, and compatibility of passive components integration. However, compared with thin film technology, the minimum thick film line width and spacing on LTCC is 4mil, which limits the packaging of fine pitch devices. In this study, one of DuPont™ photoimageable thick film gold (Au) conductors has been selected to fabricate on DuPont 951PX substrate, with the patterns as small as 1mil. Surface insulation resistance (SIR) and serpentine resistance patterns with a series of line width and spacing was printed and post fired on LTCC to investigate the capabilities and limits of the feature size. Feature dimensions were measured to compare with the design value. Metal adhesion and stud bump patterns are also included in the test substrate. After initial testing, the substrates are undergoing 300°C aging. Post aging resistance measurement, metallization adhesion pull test and Au stud bump shear test are carried out to evaluate its high temperature behaviors.