Improved stacked-diode ESD protection in nanoscale CMOS technology

Chaotic Neural Network, also denoted by the acronym CNN, has rich dynamical behaviors that can be harnessed in promising engineering applications. However, due to its complex synapse learning rules and network structure, it is difficult to update its synaptic weights quickly and implement its large scale physical circuit. This paper addresses an implementation scheme of a novel CNN with memristive neural synapses that may provide a feasible solution for further development of CNN. Memristor, widely known as the fourth fundamental circuit element, was theoretically predicted by Chua in 1971 and has been developed in 2008 by the researchers in Hewlett-Packard Laboratory. Memristor based hybrid nanoscale CMOS technology is expected to revolutionize the digital and neuromorphic computation. The proposed memristive CNN has four significant features: (1) nanoscale memristors can simplify the synaptic circuit greatly and enable the synaptic weights update easily; (2) it can separate stored patterns from superimposed input; (3) it can deal with one-to-many associative memory; (4) it can deal with many-to-many associative memory. Simulation results are provided to illustrate the effectiveness of the proposed scheme.

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Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

IEEE Transactions on Electron Devices ◽

10.1109/16.662790 ◽

1998 ◽

Vol 45 (4) ◽

pp. 849-860 ◽

Cited By ~ 26

Author(s):

Ming-Dou Ker

Keyword(s):

Low Voltage ◽

Cmos Technology ◽

High Current ◽

Esd Protection ◽

Submicron Cmos

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Cell-Based ESD Diodes with a Zigzag-Shaped Layout to Enhance the ESD Survival Level

Journal of Circuits System and Computers ◽

10.1142/s0218126617500232 ◽

2016 ◽

Vol 26 (02) ◽

pp. 1750023

Author(s):

Minoh Son ◽

Changkun Park

Keyword(s):

Integrated Circuits ◽

Cmos Technology ◽

Thermal Source ◽

Esd Protection ◽

A Cell ◽

Protection Devices ◽

Layout Technique ◽

Typical Layout ◽

Zigzag Shape ◽

Survival Level

In this study, we propose cell-based diodes which are laid out with a zigzag shape as electrostatic discharge (ESD) protection elements to enhance the ESD survival level of the diodes. Generally, diodes are regarded as simple ESD protection devices in integrated circuits. During ESD events, the P–N junction of the ESD diode acts as a thermal source. In this study, we investigate a distributed layout method which relies on a cell-based ESD diode to prevent an excessive increase in the temperature at the P–N junction. However, although the distributed layout enhances the ESD survival levels of the ESD diode, the required area increases compared that of a typical layout. Thus, we propose a zigzag layout technique for the cell-based diode to reduce the area and obtain a high ESD survival level. To verify the feasibility of the zigzag layout techniques for cell-based diodes, we designed ESD diodes using 110[Formula: see text]nm RF CMOS technology. The experimental results successfully demonstrate the feasibility of the proposed method.

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