Vertical SCR structure for on-chip ESD protection in nanoscale CMOS technology

2015 IEEE 22nd International Symposium on the Physical and Failure Analysis of Integrated Circuits ◽

10.1109/ipfa.2015.7224380 ◽

2015 ◽

Author(s):

Chun-Yu Lin ◽

Pin-Hsin Chang ◽

Rong-Kun Chang ◽

Ming-Dou Ker ◽

Wen-Tai Wang

Keyword(s):

Cmos Technology ◽

Nanoscale Cmos ◽

Esd Protection ◽

On Chip

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New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. ◽

10.1109/apccas.2004.1413010 ◽

2005 ◽

Author(s):

Ming-Dou Ker ◽

Kuo-Chun Hsu

Keyword(s):

Cmos Technology ◽

Design Concept ◽

Nanoscale Cmos ◽

Esd Protection ◽

Protection Circuits ◽

On Chip

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P-45: On-Chip ESD Protection Design for UXGA/HDTV LCoS in 0.35-μm CMOS Technology

SID Symposium Digest of Technical Papers ◽

10.1889/1.1830999 ◽

2004 ◽

Vol 35 (1) ◽

pp. 404

Author(s):

Ming-Dou Ker ◽

Shih-Hung Chen ◽

Tang-Kui Tseng

Keyword(s):

Cmos Technology ◽

Esd Protection ◽

On Chip

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ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2005.857349 ◽

2005 ◽

Vol 40 (11) ◽

pp. 2329-2338 ◽

Cited By ~ 7

Author(s):

Ming-Dou Ker ◽

K.-H. Lin

Keyword(s):

Cmos Technology ◽

Nanoscale Cmos ◽

Esd Protection

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ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-<tex>$muhbox m$</tex>Salicided CMOS Technology

IEEE Transactions on Semiconductor Manufacturing ◽

10.1109/tsm.2005.845100 ◽

2005 ◽

Vol 18 (2) ◽

pp. 328-337 ◽

Cited By ~ 21

Author(s):

M.-D. Ker ◽

C.-H. Chuang ◽

W.-Y. Lo

Keyword(s):

Cmos Technology ◽

Esd Protection ◽

On Chip

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On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476) ◽

10.1109/eosesd.2000.890086 ◽

2002 ◽

Author(s):

Tai-Ho Wang ◽

Ming-Dou Ker

Keyword(s):

Smart Card ◽

Cmos Technology ◽

Esd Protection ◽

On Chip

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ESD protection design for radio-frequency integrated circuits in nanoscale CMOS technology

2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013) ◽

10.1109/nano.2013.6720810 ◽

2013 ◽

Author(s):

Chun-Yu Lin ◽

Li-Wei Chu ◽

Shiang-Yu Tsai ◽

Ming-Dou Ker ◽

Ming-Hsiang Song ◽

...

Keyword(s):

Integrated Circuits ◽

Radio Frequency ◽

Cmos Technology ◽

Radio Frequency Integrated Circuits ◽

Nanoscale Cmos ◽

Esd Protection

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K-band low-noise amplifier with stacked-diode ESD protection in nanoscale CMOS technology

2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) ◽

10.1109/ipfa.2017.8060074 ◽

2017 ◽

Cited By ~ 1

Author(s):

Meng-Ting Lin ◽

Chun-Yu Lin

Keyword(s):

Cmos Technology ◽

Low Noise ◽

Low Noise Amplifier ◽

Nanoscale Cmos ◽

Esd Protection ◽

Noise Amplifier ◽

K Band

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Improved stacked-diode ESD protection in nanoscale CMOS technology

IEICE Electronics Express ◽

10.1587/elex.14.20170570 ◽

2017 ◽

Vol 14 (13) ◽

pp. 20170570-20170570 ◽

Cited By ~ 5

Author(s):

Chun-Yu Lin ◽

Meng-Ting Lin

Keyword(s):

Cmos Technology ◽

Nanoscale Cmos ◽

Esd Protection

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On-chip HBD sensor for nanoscale CMOS technology

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2012.6292050 ◽

2012 ◽

Cited By ~ 2

Author(s):

Ho Joon Lee ◽

Yong-Bin Kim ◽

Kyung Ki Kim

Keyword(s):

Cmos Technology ◽

Nanoscale Cmos ◽

On Chip

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ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Proceedings of the 2001 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2001 (Cat. No.01TH8548) ◽

10.1109/ipfa.2001.941461 ◽

2002 ◽

Cited By ~ 1

Author(s):

Ming-Dou Ker ◽

Che-Hao Chuang

Keyword(s):

Cmos Technology ◽

Esd Protection ◽

On Chip

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