Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

1998 ◽  
Vol 45 (4) ◽  
pp. 849-860 ◽  
Author(s):  
Ming-Dou Ker
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
High Current ◽  
Esd Protection ◽  
Submicron Cmos

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

2009 ◽  
Vol 40 (6) ◽  
pp. 1007-1012 ◽  
Author(s):  
Yongseo Koo ◽  
Kwangyeob Lee ◽  
Kuidong Kim ◽  
Jongki Kwon
Keyword(s):  
Cmos Technology ◽  
Deep Submicron ◽  
Protection Device ◽  
Esd Protection ◽  
Submicron Cmos

scholarly journals Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

2020 ◽  
Vol 15 (1) ◽  
Author(s):  
Ruibo Chen ◽  
Hongxia Liu ◽  
Wenqiang Song ◽  
Feibo Du ◽  
Hao Zhang ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Triggering Mechanism ◽  
Esd Protection ◽  
Tcad Simulation ◽  
P Type ◽  
28 Nm ◽  
Latch Up

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

scholarly journals Towards Realization of a Low-Voltage Class-AB VCII with High Current Drive Capability

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2303
Author(s):  
Leila Safari ◽  
Gianluca Barile ◽  
Vincenzo Stornelli ◽  
Shahram Minaei ◽  
Giuseppe Ferri
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Cmos Technology ◽  
Current Drive ◽  
Total Power ◽  
High Signal ◽  
High Current ◽  
Class Ab ◽  
Total Power Consumption

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V. The small signal impedance values were 973 Ω, 120 kΩ and 217 Ω at Y, X and Z ports, respectively. The maximum current at the X port was ±10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (IB) of 29 µA and output current at the X port (IX) of 10 mA, the current drive capability (IX/IB) of about 345 was achieved at the X port. The voltage swing at the Z port was (−0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 µW.

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