Rapid Thermal Processing for High-Speed III-V Compound Devices

1987 ◽  
Vol 92 ◽  
Author(s):  
M. Kuzuhara
Keyword(s):  
Integrated Circuits ◽  
Thermal Processing ◽  
High Speed ◽  
Rapid Thermal Processing ◽  
Industrial Applications ◽  
Electrical Activation ◽  
High Dose ◽  
Type Contact ◽  
Primary Focus ◽  
Compound Materials

ABSTRACTRecent activities in rapid thermal processing on III-V compound materials are reviewed with primary focus on its application to high-speed GaAs integrated circuits. Advantages of the rapid thermal processing are discussed, from the viewpoint of doping characteristics obtained both for n-type channel implants and for high dose n-type contact implants. Enhanced electrical activation is demonstrated by optimizing the encapsulating material employed for annealing high-dose Si implants. Not only these advantages, but also several problems, which should be solved before this technology can be fully utilized in industrial applications, are discussed. Special attention is devoted to improvement in the activation uniformity over a complete 2 inch diameter GaAs wafer.

Ripple Technique; a Novel Non-Contact Wafer Emissivity and Temperature Method for RTP

1991 ◽  
Vol 224 ◽  
Author(s):  
C. Schietinger ◽  
B. Adams ◽  
C. Yarling
Keyword(s):  
Optical Fiber ◽  
Measurement Technique ◽  
Thermal Processing ◽  
High Speed ◽  
Rapid Thermal Processing ◽  
Wafer Surface ◽  
Speed Measurement ◽  
Temperature Method ◽  
Emissivity Measurement ◽  
Emissivity Measurements

AbstractA novel wafer temperature and emissivity measurement technique for rapid thermal processing (RTP) is presented. The ‘Ripple Technique’ takes advantage of heating lamp AC ripple as the signature of the reflected component of the radiation from the wafer surface. This application of Optical Fiber Thermometry (OFT) allows high speed measurement of wafer surface temperatures and emissivities. This ‘Ripple Technique’ is discussed in theoretical and practical terms with wafer data presented. Results of both temperature and emissivity measurements are presented for RTP conditions with bare silicon wafers and filmed wafers.

An Electrical Characterization of Sol Films Using Devices Formed by Oxygen Implant and Rapid Thermal Processing

1987 ◽  
Vol 92 ◽  
Author(s):  
Jim D. Whitfield ◽  
Marie E. Burnham ◽  
Charles J. Varker ◽  
Syd.R. Wilson
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
High Energy ◽  
Thermally Grown Oxide ◽  
Silicon On Insulator ◽  
Wafer Surface ◽  
High Dose ◽  
Active Device ◽  
Insulating Layer ◽  
Oxygen Implantation

The advantages of Silicon-on-Insulator (SO) devices over bulk Silicon devices are well known (speed, radiation hardened, packing density, latch up free CMOS,). In recent years, much effort has been made to form a thin, buried insulating layer just below the active device region. Several approaches are being developed to fabricate such a buried insulating layer. One viable approach is by high dose, high energy oxygen implantation directly into the silicon wafer surface (1-3). With proper implant and annealing conditions, a thin stoichiometric buried oxide with a good crystalline quality silicon overlayer can be formed on which an epitaxial layer can be grown and functional devices and circuits built. As SO1 circuits become market viable, mass production tools and techniques are being developed and evaluated. Of particular interest here is the evaluation of high current oxygen implantation with rapid thermal processing on the electrical characteristics of the oxide-silicon interfaces, the silicon overlayer and the thermally grown oxide on the top surface using measurements on gated diodes and guarded capacitors.

Precipitation in silicon-on-insulator material during high- temperature annealing

1987 ◽  
Vol 45 ◽  
pp. 254-255
Author(s):  
S. J. Krause ◽  
C. O. Jung ◽  
S.R. Wilson
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Annealing Time ◽  
High Speed ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Precipitate Size ◽  
High Dose ◽  
High Temperature Annealing ◽  
Implantation Energy

Silicon-on-insulator (SOI) structure by high dose oxygen implantation (SIMOX) has excellent potential for use in radiation hardened and high speed integrated circuits. Device fabrication in SIMOX requires a high quality superficial Si layer above the buried oxide layer. Previously we reported on the effect of heater temperature, background doping, and annealing cycle on precipitate size, density, and location in the superficial Si layer. Precipitates were not eliminated with our processing conditions, but various authors have recently reported that high temperature annealing of SIMOX, from 1250°C to 1405°C, eliminates virtually all precipitates in the superficial Si layer. However, in those studies there were significant differences in implantation energy and dose and also annealing time and temperature. Here we are reporting on the effect of annealing time and temperature on the formation and changes in precipitates.

Heavy Phosphorus Implantation of Ge0.83Si0.17 Epitaxial Layers

1985 ◽  
Vol 45 ◽  
Author(s):  
J.C. Bean ◽  
A.T. Fiory ◽  
L.C. Hopkins
Keyword(s):  
Thermal Processing ◽  
Electrical Transport ◽  
Room Temperature ◽  
Molecular Beam ◽  
Secondary Ion Mass Spectrometry ◽  
Solid Phase ◽  
Rapid Thermal Processing ◽  
Electrical Activation ◽  
Temperature Dependent ◽  
Secondary Ion

ABSTRACTEpitaxial Ge-Si alloy films were grown on Si(100) by molecular beam epitaxy, subsequently given a shallow P implant, and subjected to rapid thermal processing. Heat treatment causes solid-phase epitaxial regrowth of the amorphized implanted layer similar to the case of pure Ge. Phosphorus redistribution, loss, and trapping at the Ge-Si/Si interface are also observed. Anomalous electrical activation is observed for P concentrations below 1 at.%, where the-carriers are either trapped or compensated at room temperature, but not below 100K. Analyses were carried out by Rutherford backscattering and channeling, secondary ion mass spectrometry, and temperature-dependent electrical transport.

Ultra-Shallow Diffused Emitter-Base Profiles Fabricated by Rapid Thermal Processing for High Speed Bipolar Devices

1989 ◽  
Vol 146 ◽  
Author(s):  
J. E. Urner ◽  
C. I. Drowley ◽  
P. Vande Voorde ◽  
A. Kermani
Keyword(s):  
Thermal Processing ◽  
High Speed ◽  
Boron Concentration ◽  
Secondary Ion Mass Spectrometry ◽  
Rapid Thermal Processing ◽  
Depth Resolution ◽  
Device Fabrication ◽  
Bipolar Devices ◽  
Polysilicon Emitter ◽  
Secondary Ion

ABSTRACTThe development of next-generation high-speed bipolar devices depends critically on reproducible shallow dopant profiles, with base and emitter widths considerably less than 1000 Angstroms. Sequential diffusion of boron and arsenic from implanted polysilicon is a promising means of producing such shallow emitter-base profiles. The restricted thermal budget required to reproducibly form such shallow junctions severely limits the use of conventional furnaces. We report the formation of extremely shallow emitter-base profiles using rapid thermal processing (RTP) in a double-diffused polysilicon emitter process. Polysilicon was implanted with various doses of BF2 and subjected to a conventional furnace anneal at 900ºC. This process was followed by As implantation and furnace anneal at 900ºC or RTP at 10500C or 1100ºC. A range of emitter-base profiles was generated with emitter and base widths ranging from 350-800A. Emitter-base profiles were measured using low-energy Secondary Ion Mass Spectrometry (SIMS), after removal of the polysilicon to improve depth resolution. Deconvolution of the instrumental broadening function allowed extraction of base and emitter widths as well as the boron concentration in the base. Variation of the profiles is discussed as a function of anneal times and implant dose. Modified SUPREM III parameters are obtained for diffusivities under these RTP conditions. The implications for high speed bipolar device fabrication will be presented.

Characterisation of Low Energy Boron Implantation and Fast Ramp-Up Rapid Thermal Annealing

1998 ◽  
Vol 525 ◽  
Author(s):  
E. J. H. Collart ◽  
G. de Cock ◽  
A. J. Murrell ◽  
M. A. Foad
Keyword(s):  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Low Energy ◽  
Electrical Activation ◽  
Junction Depth ◽  
Boron Implantation

ABSTRACTThe effects of ramp-up rate during rapid thermal processing of ultra-shallow boron implants have been investigated. Ramp-up rates were varied between 25 °C and 200 °C for two types of anneals: soak anneals and spike anneals. It was found that the ramp-up rate had very little influence on junction depth or electrical activation for both types of anneals. Spike anneals did produce shallower profiles than soak anneal for a comparable electrical activation and may be an option for future processes.

Rapid Thermal Processing of Gate Dielectric Films and their Characterization

1987 ◽  
Vol 92 ◽  
Author(s):  
D. L. Flowers ◽  
J. Nulman ◽  
J. P. Krusius
Keyword(s):  
Integrated Circuits ◽  
Thermal Processing ◽  
Gate Dielectric ◽  
Defect Density ◽  
Rapid Thermal Processing ◽  
Dielectric Films ◽  
Mobile Charge ◽  
High Quality ◽  
Temperature Constraint ◽  
Low Levels

ABSTRACTRapid thermal processing has been used to grow high quality, low defect density, low mobile charge, dielectric films of oxide and nitrided oxide. Suitable annealing can lower the fixed charge and interfacial trap density present in these filmsto acceptably low levels. Both RTA and RTN were shown to improve the dielectric properties of the grown oxides. These filmsshould be strong candidates for use in high density, shallow junction, integrated circuits where a minimal time/temperature constraint is imposed on further processing after diffusion.

Indium in silicon: a study on diffusion and electrical activation.

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Scalese ◽  
A. La Magna ◽  
G. Mannino ◽  
V. Privitera ◽  
M. Bersani ◽  
...  
Keyword(s):  
Band Gap ◽  
Carrier Concentration ◽  
Silicon Substrate ◽  
Thermal Processing ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Electrical Activation ◽  
Fixed Dose ◽  
Active Fraction

AbstractIn this work we investigate the diffusion and the electrical activation of In atoms implanted in silicon with different energies, in the range 80-360 keV, after rapid thermal processing. Our investigation shows a clear dependence of In out-diffusion and electrical activation on the implant depth, being the electrically active fraction higher with increasing the implant energy for a fixed dose. The data are explained considering the balance between the local In concentration and the C background inside the silicon substrate and the formation of C-In complexes, which play a role in the enhanced electrical activation due to the shallower level they introduce into the Si band gap (Ev+0.111 eV), with respect to the rather deep level (Ev+0.156 eV) of In alone. In and C co-implantation has also been studied within this work, in order to confirm the key role of C in the increase of the electrical activation. A large increase of the electrical activation has been detected in the co-implanted samples, up to a factor of about 8 after annealing at 900°C. However, C precipitation occurs at 1100°C, with dramatic effects on the carrier concentration.

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