Indium in silicon: a study on diffusion and electrical activation.

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Scalese ◽  
A. La Magna ◽  
G. Mannino ◽  
V. Privitera ◽  
M. Bersani ◽  
...  
Keyword(s):  
Band Gap ◽  
Carrier Concentration ◽  
Silicon Substrate ◽  
Thermal Processing ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Electrical Activation ◽  
Fixed Dose ◽  
Active Fraction

AbstractIn this work we investigate the diffusion and the electrical activation of In atoms implanted in silicon with different energies, in the range 80-360 keV, after rapid thermal processing. Our investigation shows a clear dependence of In out-diffusion and electrical activation on the implant depth, being the electrically active fraction higher with increasing the implant energy for a fixed dose. The data are explained considering the balance between the local In concentration and the C background inside the silicon substrate and the formation of C-In complexes, which play a role in the enhanced electrical activation due to the shallower level they introduce into the Si band gap (Ev+0.111 eV), with respect to the rather deep level (Ev+0.156 eV) of In alone. In and C co-implantation has also been studied within this work, in order to confirm the key role of C in the increase of the electrical activation. A large increase of the electrical activation has been detected in the co-implanted samples, up to a factor of about 8 after annealing at 900°C. However, C precipitation occurs at 1100°C, with dramatic effects on the carrier concentration.

Rapid-Thermal-Processing Induced Deep Level Traps and their Spatial Distribution in MBE GaAs

1987 ◽  
Vol 92 ◽  
Author(s):  
Akio Kitagawa ◽  
Yutaka Tokuda ◽  
Akira Usami ◽  
Takao Wada ◽  
Hiroyuki kano
Keyword(s):  
Thermal Processing ◽  
Deep Level Transient Spectroscopy ◽  
Molecular Beam ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Spatial Variations ◽  
Molecular Beam Epitaxial ◽  
Gaas Films ◽  
Si Doped ◽  
Transient Spectroscopy

ABSTRACTRapid thermal processing (RTP) using halogen lamps for a Si-doped molecular beam epitaxial (MBE) n-GaAs layers was investigated by deep level transient spectroscopy. RTP was performed at 700°C, 800°C and 900°C for 6 s. Two electron traps NI ( Ec-0.5-0.7eV) and EL2 (Ec - 0.82 eV) are produced by RTP at 800 and 900°C.The peculiar spatial variations of the Nl and EL2 concentration across the MBE GaAs films are observed. The larger concentrations of the trap N1 and EL2 are observed near the edge of the samples, and the minima of N1 and EL2 concentration lie between the center and the edge of the sample. It seems that these spatial variations of N1 and EL2 concentration are consistent with that of the thermal stress induced by RTP. Furthermore, the EL2 concentration near the edge of the sample is suppressed by the contact with the GaAs pieces on the edge around the sample during RTP.

Ion Implantation-Induced Defects and the Influence of Titanium Silicidation

1998 ◽  
Vol 510 ◽  
Author(s):  
D.Z. Chi ◽  
S. Ashok ◽  
D. Theodore
Keyword(s):  
Ion Implantation ◽  
Thermal Processing ◽  
Thermal Evolution ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Thermal Signature ◽  
P Type ◽  
Induced Defects

AbstractThermal evolution of ion implantation-induced defects and the influence of concurrent titanium silicidation in pre-amorphized p-type Si (implanted with 25 KeV, 1016 cm2Si+) under rapid thermal processing (RTP) have been investigated. Presence of implantation-induced electrically active defects has been confirmed by current-voltage (IV) and deep level transient spectroscopy (DLTS) measurements. DLTS characterization results show that the evolution of electrically active defects in the Si implanted samples under RTP depend critically on the RTP temperature: Hole traps HI (0.33 eV) and H4 (0.47 eV) appear after the highest temperature (950 °C) anneal, while a single trap H3 (0.26 eV) shows up at lower anneal temperatures (≤ 900 °C). The thermal signature of H4 defect is very similar to that of the iron interstitial while those of HI and H3 levels appear to originate from some interstitial-related defects, possibly complexes. A most interesting finding is that the above interstitial related defects can be eliminated completely with Ti silicidation, apparently a result of vacancy injection. However the silicidation process itself introduces a new H2 (0.30 eV) level, albeit at much lower concentration. This same H2 level is also seen in unimplanted samples under RTP. The paper will present details of defect evolution under various conditions of RTP for samples with and without the self-implantation and silicidation.

Effects of Rapid Thermal Processing on SiO2/GaAs Interfaces

1988 ◽  
Vol 126 ◽  
Author(s):  
Yutaka Tokuda ◽  
Masayuki Katayama ◽  
Nobuo Ando ◽  
Akio Kitagawa ◽  
Akira Usami ◽  
...  
Keyword(s):  
Outer Surface ◽  
Photoelectron Spectroscopy ◽  
Thermal Processing ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Rf Sputtering ◽  
Electron Traps ◽  
Conventional Furnace ◽  
Pile Up ◽  
Transient Spectroscopy

ABSTRACTEffects of rapid thermal processing (RTP) on SiO2/GaAs interfaces have been investigated with Auger electron spectroscopy and X-ray photoelectron spectroscopy. SiO2 films of 100, 175, 200 and 1250 nm thickness have been deposited on liquid encapsulated Czochralski-grown (100) n-type GaAs wafers by the RF sputtering method. RTP has been performed at 800°C for 6 s. For comparison, conventional furnace processing (CFP) has also been performed at 800°C for 20 min for 200-nm-thick SiO2/GaAs. The Ga is observed on the outer SiO2 surface for RTP samples as well as CFP samples. This indicates that the outdiffusion of Ga occurs after only 6 s at 800°C even through 1250-nm-thick SiO2 films. The depth profile of Ga reveals the pile-up of Ga on the outer SiO2 surface for both RTP and CFP samples. The amount of Ga on the outer surface gradually increases in the thickness range 1250 to 175 nm. The As is also observed on the outer surface. The amount of Ga and As on the outer surface rapidly increases at 100 nm thickness. Electron traps in RTP samples have been studied with deep-level transient spectroscopy. Different electron traps are produced in GaAs by RTP between 100-nm- and 200-nm-thick SiO2/GaAs. It is thought that the production of different traps by RTP is related to the amount of Ga and As loss through SiO2 films from GaAs.

Role of the carbon source in the transformation of amorphous carbon to graphene during rapid thermal processing

2019 ◽  
Vol 21 (18) ◽  
pp. 9384-9390 ◽  
Author(s):  
Xiaowei Li ◽  
Yong Zhou ◽  
Xiaowei Xu ◽  
Aiying Wang ◽  
Kwang-Ryeol Lee
Keyword(s):  
Carbon Source ◽  
Amorphous Carbon ◽  
Thermal Processing ◽  
Rapid Thermal Processing

A fast transfer-free synthesis of a graphene structure can be successfully achieved by Ni-catalysed transformation of amorphous carbon (a-C) during rapid thermal processing, but the role of the a-C structure in the a-C-to-graphene transformation is still unclear.

The Role of Thermal Radiative Properties of Semiconductor Wafers in Rapid Thermal Processing

1996 ◽  
Vol 429 ◽  
Author(s):  
P. J. Timans
Keyword(s):  
Thermal Processing ◽  
Radiation Heat Transfer ◽  
Rapid Thermal Processing ◽  
Device Fabrication ◽  
Radiative Properties ◽  
Thermal Radiative Properties ◽  
Wide Range ◽  
Basic Physics ◽  
Key Issues

AbstractRapid thermal processing (RTP) has become a key technology in the fabrication of advanced semiconductor devices. As RTP becomes the accepted technique for an increasingly wide range of processes in device fabrication, the understanding of the basic physics of radiation heat transfer in RTP systems is also being extended rapidly. This paper illustrates the use of optical models for prediction of the thermal radiative properties of semiconductor wafers. Such calculations can be used to address many of the key issues of interest in RTP, including questions concerning temperature measurement and process repeatability.

The Control and Impact of Processing Ambient During RTP

1998 ◽  
Vol 514 ◽  
Author(s):  
Karen Maex ◽  
Eiichi Kondoh ◽  
Anne Lauwers ◽  
Muriel DePotter ◽  
Joris Prost
Keyword(s):  
Thermal Processing ◽  
Thermal Process ◽  
Rapid Thermal Processing ◽  
Process Window ◽  
Temperature Uniformity ◽  
Silicide Formation ◽  
Temperature Variations ◽  
Set Up ◽  
Interconnect Technology

ABSTRACTThe introduction of rapid thermal processing for silicide formation has triggered a lot of research to temperature uniformity and reproducibility in RTP systems. From the other side there has been the demand to make the process itself as robust as possible for temperature variations. Indeed the way the module is set up can open or close the thermal process window for silicidation. In addition to the temperature, the ambient control is to be taken into account. Although gasses are specified to a low level of contaminants, the RTP step needs to be optimized for optimal contaminant reduction. Besides, the process wafer itself can be a source of contamination. In this paper an overview will be given of the role of temperature and ambient during RTP on the silicidation processes. The effect of the wafer on ambient purity will be highlighted. It will be shown that the latter can also have an impact on other process steps in the interconnect technology.

Role of C and Ge in the electrical activation of In implanted in Silicon

2004 ◽  
Vol 810 ◽  
Author(s):  
S. Scalese ◽  
V. Privitera ◽  
M. Italia ◽  
A. La Magna ◽  
P. Alippi ◽  
...  
Keyword(s):  
Experimental Study ◽  
Silicon Substrate ◽  
Electrical Activation ◽  
Limiting Factor ◽  
Thermal Processes ◽  
Critical Issues ◽  
First Time ◽  
And Diffusion ◽  
Post Implantation

ABSTRACTAn experimental study on In implantation in Si was performed, considering some factors that affect its electrical activation. One of the critical issues concerning In is represented by its outdiffusion, during the post-implantation annealing, a limiting factor to get active In concentration suitable for applications in microelectronics. The use of different thermal processes was evaluated, aimed to achieve a reduction of the outdiffusion and an increase of the electrical activation of In in silicon. The influence of the substrate purity on the electrical activation was shown to be of great importance: in particular, it was shown that C., present in the silicon substrate as a contaminant or as a co-implanted species, has a key-role in the electrical activation and diffusion of In in silicon. Furthermore, for the first time at our knowledge, the behaviour of In implanted in Si1−xGex layers grown by CVD on Si wafers was investigated, for Ge concentration of 0.5% and 1%. An enhancement in the electrical activation was observed with increasing the Ge content in the alloy.

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