Mechanism of Dopant Activation Enhancement in Shallow Junctions by Hydrogen

2005 ◽  
Vol 864 ◽  
Author(s):  
A. Vengurlekar ◽  
S. Ashok ◽  
Christine. E. Kalnas ◽  
H. Win Ye
Keyword(s):  
Atomic Hydrogen ◽  
Annealing Temperature ◽  
Process Integration ◽  
Hydrogen Plasma ◽  
Cmos Technology ◽  
Dopant Activation ◽  
Enhanced Diffusion ◽  
Device Scaling ◽  
High K ◽  
Shallow Junctions

AbstractThe ability to activate greater amounts of dopants is a significant challenge for the realization of shallow junctions in device scaling for Si CMOS technology. Dopant activation is difficult to achieve in shallow junctions due to higher concentrations of dopants and possible formation of dopant clusters. The high temperatures currently used to activate dopants result in increased junction depth and process integration issues with high-k dielectrics. However, lowering the annealing temperature results in lesser dopant activation and problems with transient enhanced diffusion. Our previous work reported on the enhancement of activation in boron implanted at a dose of 5E14/cm2 and annealed at temperatures of 450 °C and below, by the incorporation of atomic hydrogen introduced by exposing the substrate to a hydrogen plasma at 250 °C. In this work, further experiments have been carried out to get a better understanding of the mechanisms responsible for boron activation enhancement. Hydrogen-related activation was studied in boron, phosphorus and antimony implanted samples. The experimental results shed new light on the interactions among atomic hydrogen, point defects and dopants.

Enhancement of Boron Activation in Shallow Junctions by Hydrogen

2004 ◽  
Vol 810 ◽  
Author(s):  
A. Vengurlekar ◽  
S. Ashok ◽  
C. E. Kalnas ◽  
N. D. Theodore
Keyword(s):  
Atomic Hydrogen ◽  
Electron Cyclotron Resonance ◽  
Hydrogen Plasma ◽  
Cluster Formation ◽  
Relaxation Effect ◽  
Lattice Relaxation ◽  
Hydrogen Incorporation ◽  
Device Scaling ◽  
Shallow Junctions ◽  
Lower Temperature

ABSTRACTThe ability to activate greater amounts of dopants at lower temperatures is a persistent contingency in the continual drive for device scaling in Si microelectronics. We report on the effect of incorporating atomic hydrogen on the activation of implanted boron in shallow junctions. Hydrogen incorporation into the sample was carried out by exposure to an electron cyclotron resonance (ECR) hydrogen plasma. Enhanced activation was observed in hydrogenated samples for post-implantation annealing temperatures of 450°C and below, as measured by spreading resistance profilometry, and confirmed by identical boron atomic profile in hydrogenated and unhydrogenated samples. The enhancement in boron activation at lower temperature is attributed to the creation of vacancies in the boron-implanted region, the lattice-relaxation effect by the presence of atomic hydrogen, and the effect of atomic hydrogen on boron-interstitial cluster formation.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

scholarly journals Coverage Layout Design Rules and Insertion Utilities for CMP-Related Processes

2020 ◽  
Vol 11 (1) ◽  
pp. 2
Author(s):  
Eitan N. Shauly ◽  
Sagee Rosenthal
Keyword(s):  
Integrated Circuit ◽  
Thermal Effects ◽  
Process Integration ◽  
Proximity Effects ◽  
Published Data ◽  
Metal Gate ◽  
Comprehensive Description ◽  
Advanced Technologies ◽  
High K ◽  
Rf Devices

The continuous scaling needed for higher density and better performance has introduced some new challenges to the planarity processes. This has resulted in new definitions of the layout coverage rules developed by the foundry and provided to the designers. In advanced technologies, the set of rules considers both the global and the local coverage of the front-end-of line (FEOL) dielectric layers, to the back-end-of-line (BEOL) Cu layers and Al layers, to support high-k/Metal Gate process integration. For advance technologies, a new set of rules for dummy feature insertion was developed by the integrated circuit (IC) manufacturers in order to fulfill coverage limits. New models and utilities for fill insertion were developed, taking into consideration the design coverage, thermal effects, sensitive signal line, critical analog and RF devices like inductors, and double patterning requirements, among others. To minimize proximity effects, cell insertion was also introduced. This review is based on published data from leading IC manufacturers with a careful integration of new experimental data accumulated by the authors. We aim to present a typical foundry perspective. The review provides a detailed description of the chemical mechanical polishing (CMP) process and the coverage dependency, followed by a comprehensive description of coverage rules needed for dielectric, poly, and Cu layers used in advanced technologies. Coverage rules verification data are then presented. RF-related aspects of some rules, like the size and the distance of dummy features from inductors, are discussed with additional design-for-manufacturing layout recommendations as developed by the industry.

Effects of Carbon Co-Implantation on Transient Enhanced Diffusion and Performances of the Phosphorus Doped Ultra-Shallow Junction Nano NMOSFET

2013 ◽  
Vol 284-287 ◽  
pp. 98-102
Author(s):  
Hung Yu Chiu ◽  
Yean Kuen Fang ◽  
Feng Renn Juang
Keyword(s):  
Cmos Technology ◽  
Shallow Junction ◽  
Enhanced Diffusion ◽  
Transient Enhanced Diffusion ◽  
Technology Applications ◽  
Implantation Process ◽  
Phosphorus Doped

The carbon (C) co-implantation and advanced flash anneal were employed to form the ultra shallow junction (USJ) for future nano CMOS technology applications. The effects of the C co-implantation process on dopant transient enhanced diffusion (TED) of the phosphorus (P) doped nano USJ NMOSFETs were investigated in details. The USJ NMOSFETs were prepared by a foundry’s 55 nano CMOS technology. Various implantation energies and doses for both C and P ions were employed. Results show the suppression of the TED is strongly dependent on both C and P implantation conditions. Besides, the mechanisms of P TED and suppression by C ion co-implantation were illustrated comprehensively with schematic models.

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