Activation of Implanted Poly Gates by Short Cycle Time Annealing

2000 ◽  
Vol 610 ◽  
Author(s):  
A. T. Fiory ◽  
K. K. Bourdelle
Keyword(s):  
Chemical Vapor ◽  
Maximum Temperature ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Thermal Oxide ◽  
Van Der Pauw ◽  
P Type ◽  
Temperature Time ◽  
And Diffusion ◽  
Secondary Ion

AbstractAmorphous silicon films with B, P, and As implants were activated with thermal anneals that include spiking to the maximum temperature. Films were grown over thermal oxide by chemical vapor deposition as two separately implanted 50-nm layers for manipulating dopant placement and diffusion. Electrical activation was determined by Hall van der Pauw and MOS C-V, and dopant diffusion was profiled by secondary ion mass spectroscopy (SIMS). Flat-band voltage was used to benchmark relative thermal budgets for p-type poly. Temperature-time relationships are used to deduce effective activation energies.

Flat-band Voltage Study Of Atomic-layer-Deposited Aluminum-oxide Subjected To Spike Thermal Annealing

2003 ◽  
Vol 765 ◽  
Author(s):  
V. R. Mehta ◽  
A. T. Fiory ◽  
N. M. Ravindra ◽  
M. Y. Ho ◽  
G. D. Wilk ◽  
...  
Keyword(s):  
Atomic Layer ◽  
Oxide Thickness ◽  
Atomic Diffusion ◽  
Flat Band ◽  
Gate Electrodes ◽  
Layer Deposition ◽  
Thermal Oxide ◽  
P Type ◽  
Low Thermal Budget ◽  
Spike Annealing

AbstractHigh-κ dielectrics based the oxide of Al were prepared by atomic layer deposition (ALD) on 200-mm p-type Si wafers. Films were deposited directly on clean Si or on 0.5-nm underlayers of rapid thermal oxide or oxynitrides grown in O2 and/or NO ambients. The purpose of the underlayer films is to provide a barrier for atomic diffusion from the crystal Si to the high-κ dielectric film. Deposited Al-oxide films varied in thickness from 2 to 6 nm. Post deposition anneals were used to stabilize the ALD oxides. Equivalent SiO2-oxide thickness varied from 1.0 to 3.5 nm. In situ P-doped amorphous-Si 160 nm films were deposited over the oxides to prepare heavily doped n-type gate electrodes in MOS structures. Samples were rapid thermal annealed in N2 ambient at 800°C for 30 s, or spike annealed at 950, 1000, and 1050°C (nominally zero time at peak temperature). Flat band voltages, VFB were determined from C-V measurements on dot patterns. The 800°C anneals were used as a baseline, at which the poly-Si electrodes are crystallized and acquire electrical activation while subjecting the high-κ dielectrics to a low thermal budget. Positive shifts in VFB were observed, relative to a pure SiO2 control, ranging from 0.2 to 0.8 V. Spike annealing reduces the VFB shift for ALD films deposited over underlayer films. The VFB shift and the changes with annealing temperature show systematic dependence on the nitridation of the underlayer.

Phosphorus and Boron Implantation into (100) Germanium

2004 ◽  
Vol 809 ◽  
Author(s):  
Y. S. Suh ◽  
M. S. Carroll ◽  
R. A. Levy ◽  
A. Sahiner ◽  
C. A. King
Keyword(s):  
Secondary Ion Mass Spectrometry ◽  
Dopant Activation ◽  
Entire Energy Range ◽  
Entire Energy ◽  
Boron Implantation ◽  
Pearson Distributions ◽  
P Type ◽  
First Four Moments ◽  
And Diffusion ◽  
Secondary Ion

ABSTRACTBoron and phosphorus were implanted into (100) Ge with energies ranging from 20-320 keV and doses of 5×1013 to 5×1016 cm−2. The as-implanted and annealed dopant profiles were examined using secondary ion mass spectrometry (SIMS) and spreading resistance profiling (SRP). The first four moments were extracted from the as-implanted profile for modeling with Pearson distributions over the entire energy range. The samples were annealed at 400, 600, or 800°C in nitrogen ambient. The dopant activation and diffusion were also examined and it was found that p-type sheet resistances immediately after boron implantation as low as 18 ohms/sq could be obtained without subsequent annealing.

Properties Of Inp Simultaneously Doped With Zinc And Sulfur Grown By Mocvd

1996 ◽  
Vol 442 ◽  
Author(s):  
C. M. Alavanja ◽  
C. J. Pinzone ◽  
S. K. Sputz ◽  
M. Geva
Keyword(s):  
Energy Levels ◽  
Chemical Vapor ◽  
Hole Mobility ◽  
Group V ◽  
Zn Diffusion ◽  
Group Iii ◽  
Donor Acceptor ◽  
And Performance ◽  
P Type ◽  
Secondary Ion

AbstractAs the p-type dopant most often used in metalorganic chemical vapor deposition (MOCVD) of Group III - Group V compound semiconductors, Zn presents problems in device design and performance because of its high diffusivity in these materials. While Zn diffusion into n-type layers such as InP:S has been observed frequently, there is little known as to the electronic and optical properties of the resultant material. We have grown InP samples by MOCVD which are doped with both Zn and S to levels as high as 3×1018 cm−3. These samples were analyzed by electrochemical C-V profiling, van der Pauw-Hall analysis, secondary ion mass spectroscopy (SIMS), and low temperature (10K) photoluminescence spectroscopy (PL). We have determined that good hole mobility is maintained in InP:Zn samples that are simultaneously doped with S up to a level of 4×1017 cm−3. PL analysis of co-doped samples shows peaks between 0.91 and 0.92 μm which are indicative of donor-acceptor transitions, and broad peaks with energy levels of approximately 1.0 μm which may be indicative of ZnS complexes or precipitates. SIMS analysis of Zn diffusion into Fe doped substrates shows that Zn diffusion is reduced in the presence of S in the lattice.

Boron Doping using Proximity Rapid Thermal Diffusion from Spin-on-Dopants

1994 ◽  
Vol 342 ◽  
Author(s):  
M. Rastogi ◽  
W. Zagozdzon-Wosik ◽  
F. Romero-Borja ◽  
J. M. Heddleson ◽  
R. Beavers ◽  
...  
Keyword(s):  
Thermal Diffusion ◽  
Process Variables ◽  
Dopant Incorporation ◽  
Boron Doped ◽  
Doping Technique ◽  
Rapid Thermal Diffusion ◽  
P Type ◽  
Temperature Time ◽  
Secondary Ion ◽  
Dopant Source

ABSTRACTProximity rapid thermal diffusion (RTD) has been investigated as a doping technique for p-type boron doped junctions. The efficiency of RTD has been studied as a function of process variables (temperature, time, and ambient) and evaluated based on sheet resistance measurements, secondary ion mass spectroscopy (SIMS), spreading resistance (SR), and Fourier transmission infrared absorption (FTIR) in a spin-on-dopant source (SOD). The doping efficiency in source wafers is controlled by different mechanism than in processed wafers. Strong influence of dopant incorporation in the processed wafers on oxygen content in the diffusion ambient is observed especially at low diffusion temperatures.

Preparation and Characterization of Low Temperature Silicon Dioxide Thin Films Using Tetramethylsilane (TMS) for Microfabrication Applications

2001 ◽  
Vol 685 ◽  
Author(s):  
Xin Lin ◽  
Stephen J. Fonash
Keyword(s):  
Low Temperature ◽  
Silicon Dioxide ◽  
Gas Flow ◽  
Oxide Films ◽  
Annealing Treatment ◽  
Chemical Vapor ◽  
Flow Rate Ratio ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Gas Dilution

AbstractLow temperature silicon dioxide depositions have been carried out by plasma enhanced chemical vapor deposition (PECVD) using TMS as the Si precursor at 100-200°C at the pressure of 2-8 Torr. An RF power of 40 W and a TMS:O2 gas flow rate ratio of 1:500 without inert gas dilution were used in the depositions. It was found that the current-voltage (I-V) characteristics of as-deposited oxide films improved as the substrate temperature increased or deposition pressure decreased. Oxide films deposited at 2-3 Torr exhibited typical Fowler-Nordheim (F-N) tunneling characteristics and breakdown voltages greater than 8 MV/cm. The best capacitance-voltage (C-V) characteristics, giving a small flat band voltage shift, a small amount of positive oxide charge, a small hysteresis in bi-directional C-V sweep, and a low interface trap density, were obtained at 3 Torr. Post-deposition annealing in forming gas at the deposition temperature was performed and proved to be an effective approach for improving the electrical properties of the deposited oxide films without compromising the low temperature aspect of the process. By annealing at 200°C, the F-N tunneling barrier height increased by as much as 0.6 eV, the flat-band voltage and the hysteresis in C-V sweep were reduced by 0.74 V and 0.08 V, respectively. In addition, hydrogen was found to play a key role in the annealing treatment and its mechanisms were discussed.

The Characteristics of Silicon Dioxide Deposited by Inductively Coupled Plasma Chemical Vapor Deposition at 150°C

2003 ◽  
Vol 769 ◽  
Author(s):  
Su-hyuk Kang ◽  
Min-Cheol Lee ◽  
Kook-Chul Moon ◽  
Min-koo Han
Keyword(s):  
Silicon Dioxide ◽  
Inductively Coupled Plasma ◽  
Chemical Vapor ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Plasma Chemical ◽  
Silicon Dioxide Film ◽  
Plasma Chemical Vapor Deposition ◽  
Inductively Coupled ◽  
Dioxide Film

AbstractAn ultra-low temperature processed silicon dioxide film has been fabricated by inductively coupled plasma chemical vapor deposition at 150°C using He/N2O/SiH4 mixture. The deposited silicon dioxide film exhibits a high breakdown field larger than 6MV/cm in case of high ICP plasma condition while the flat band voltage of the oxide film significantly shifted in the negative direction with increasing ICP power. In order to obtain both high electrical breakdown filed and the low flat-band voltage, excimer laser irradiation with the energy density of 430mJ/cm2 is employed. The oxide film irradiated by excimer laser exhibited considerably shifted in the positive direction without scarifying the breakdown characteristics.

Flat-band Voltage Shift of MOS Capacitors with Tantalum Nitride Gate Electrodes Induced by Post Metallization Annealing

2003 ◽  
Vol 786 ◽  
Author(s):  
M. Kadoshima ◽  
K. Yamamoto ◽  
H. Fujiwara ◽  
K. Akiyama ◽  
K. Tominaga ◽  
...  
Keyword(s):  
Chemical Vapor ◽  
Tantalum Nitride ◽  
Flat Band ◽  
Processing Temperature ◽  
Flat Band Voltage ◽  
Gate Electrode ◽  
Mos Capacitors ◽  
Effective Work ◽  
Effective Work Function ◽  
Vapor Deposition Technique

ABSTRACTWe have investigated the flat-band voltage (VFB) shifts of tantalum nitride gate MOS capacitors prepared by two methods. One is CVD-tantalum nitride (CVD-TaN) deposited by the chemical vapor deposition technique using Ta[NC(CH3)2C2H5][N(CH3)2]3 as a precursor, and the other one is sputtered tantalum nitride (sp-TaN) electrodes deposited by reactive DC magnetron sputtering. In the case of the CVD-TaN electrodes, the effective work function estimated from the relationship between VFB and the equivalent oxide thickness (EOT) of the MOS capacitors was about 4.4eV after post metallization annealing (PMA) at 400°C, and shifted to the mid-gap after PMA at 950°C. Moreover, the VFB values of MOS capacitors with sp-TaN electrodes also showed the same behavior after PMA. This shift is mainly dependent on the PMA temperature, regardless of the deposition method used. Similar VFB shifts induced by PMA were also observed in sp-TaN/ Al2O3/ SiO2/ p-Si and sp-TaN/ TaOx/ SiO2/ p-Si capacitors. However, in the case of the sp-TaN/ TaOx/ SiO2/ p-Si capacitors, the VFB shift was also observed when the PDA temperature after the TaOx deposition was 800°C and the PMA temperature after the TaN deposition was only 400°C. These results strongly suggest that this VFB shift caused by the PMA originates from a thin interfacial oxide layer between the TaN gate electrode and the dielectrics. Therefore, the maximum processing temperature after gate electrode deposition is important in order to control the threshold voltage of tantalum nitride gate MOSFETs.

On the Interface Properties and Deep Level Defects in Ta2O5 Grown on Si by Plasma Enhanced Liquid Source-Cvd

1993 ◽  
Vol 309 ◽  
Author(s):  
P.A. Murawala ◽  
N. Sawai ◽  
T. Tatsuta ◽  
O. Tsuji ◽  
Sz. Fujita ◽  
...  
Keyword(s):  
Deep Level ◽  
High Stress ◽  
Chemical Vapor ◽  
Interface State ◽  
Vital Role ◽  
Deep Levels ◽  
Flat Band ◽  
Interface Properties ◽  
Flat Band Voltage ◽  
Liquid Source

AbstractWe report, for the first time, on interface properties of the Ta2O5-Si system and on the deep level defects in Ta2O5 grown by plasma enhanced liquid source chemical vapor deposition (PE-LS-CVD) using Ta(OC2Hs)5. The capacitance voltage (C–V) measurement performed on Au/Ta2O5/n, p-Si MOS diodes resulted in very well defined C-V charactristics which compares well with the ideal C-V curve. The flat band voltage is as low as 0.15 V and the minimum density of the interface state is about 2.7 × 1011 cm−2 ev−1. In order to examine deep level defects in Ta2O5, we investigated variations of flat band voltage under application of high stress electric field (10MV/cm), by which hot carriers are injected in to deep levels. This charge transfer process results in increase of charges in Ta2O5 oxide which is attributed to the equivalent deep level defect densities, which is found to be of the order of 2 × 1011 cm−2 in the Ta2O5-Si system. These results strongly suggest low interface states and deep levels in the PE-LS-CVD grown Ta2O5-Si system, which may be brought about by low decomposed-carbon impurities in the film, confirmed by AES in our previous reports. These films can play a vital role as thin capacitors in I.C. technology.

Interface morphology of thermal oxide grown on polycrystalline silicon by different processes

1992 ◽  
Vol 50 (2) ◽  
pp. 1396-1397
Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck
Keyword(s):  
Integrated Circuits ◽  
Polycrystalline Silicon ◽  
Silicon Films ◽  
Interface Morphology ◽  
Oxide Interface ◽  
Poly Silicon ◽  
Thermal Oxide ◽  
Grain Orientations ◽  
Polycrystalline Silicon Films ◽  
P Type

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.

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