The Effects of Annealing Temperature on the Characteristics of Buried Oxide Silicon-On-Insulator

1985 ◽  
Vol 53 ◽  
Author(s):  
B.-Y Mao ◽  
P.-H. Chang ◽  
H.W. Lam ◽  
B.W. Shen ◽  
J.A. Keenan
Keyword(s):  
Annealing Temperature ◽  
Silicon Film ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Thermal Donor ◽  
Buried Oxide ◽  
Lower Oxygen ◽  
Higher Temperature ◽  
Soi Substrates ◽  
Post Implantation

ABSTRACTThe effects of post implantation annealing on the properties of buried oxide silicon-on-insulator (SOI) substrates in the temperature range of 1150°C to 1300°C have been studied. Microstructural analyses showed that the crystallinity of the top silicon layer was improved at higher annealing temperature. Lower thermal donor generation at 450°C was observed in SOI annealed at higher temperature. The improvement in microstructure and lower thermal donor generation were correlated to the lower oxygen concentration in the top silicon film.

Polycrystalline Silicon Grown on Porous Silicon-on-Insulator Substrates

1996 ◽  
Vol 452 ◽  
Author(s):  
Klaus Y.J. Hsu ◽  
C. H. Lee ◽  
C. C. Yeh
Keyword(s):  
Porous Silicon ◽  
Low Temperature ◽  
Silicon Film ◽  
Silicon Layer ◽  
Porous Silicon Layer ◽  
Silicon On Insulator ◽  
Cross Sectional ◽  
Diffraction Patterns ◽  
Si Films ◽  
Soi Substrates

AbstractInexpensive full-wafer SOI substrates are appealing for various applications such as ULSI. As an attempt to achieve this goal, low-temperature deposition of silicon on novel porous Si-on-insulator (PSOI) substrates was performed in this work. The bottom insulator was obtained by anodically oxidizing a pre-formed porous silicon film in HCl solution. The thickness, uniformity and quality of the resulted bottom oxide layer as well as the residual porous silicon layer above were well-controlled. Low-temperature PECVD growth of silicon on the PSOI wafer was conducted by using the residual porous silicon as the seed. Cross-sectional TEM pictures and electron diffraction patterns showed that poly-Si films were formed on PSOI substrates under the conditions of 98% hydrogen dilution ratio, 20 Watts RF power, and 300°C substrate temperature. Further thermal annealing at 1050°C for 30 minutes significantly enhanced the crystallinity of the deposited films. Combined with the excellent insulation ability of the bottom oxide, the technique is suitable for future inexpensive full-wafer SOI fabrication.

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

ChemInform Abstract: Growth of Buried Oxide Layers of Silicon-on-Insulator (SOI) Structures by Thermal Oxidation of the Top Silicon Layer.

ChemInform ◽  
2010 ◽  
Vol 28 (43) ◽  
pp. no-no
Author(s):  
E. SCHROER ◽  
S. HOPFE ◽  
Q. Y. TONG ◽  
U. GOESELE ◽  
W. SKORUPA
Keyword(s):  
Thermal Oxidation ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Oxide Layers ◽  
Buried Oxide

The Physical and Electrical Properties of Buried Nitride Soi Structures Synthesized By Nitrogen Ion Implantation

1985 ◽  
Vol 53 ◽  
Author(s):  
C. Slawinski ◽  
B.-Y. Mao ◽  
P.-H. Chang ◽  
H.W. Lam ◽  
J.A. Keenan
Keyword(s):  
Ion Implantation ◽  
Nitrogen Concentration ◽  
Silicon Film ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Crystal Silicon ◽  
Nitrogen Ion Implantation ◽  
Donor Formation ◽  
Nitrogen Ion

ABSTRACTBuried nitride silicon-on-insulator (SOI) structures have been fabricated using the technique of nitrogen ion implantation. The crystallinity of the top silicon film was found to be exceptionally good. The minimum channeling yield, Xmin' was better than 3%. This is comparable to the value observed for single crystal silicon. The buried insulator formed during the anneals has been identified as polycrystalline α-Si3 N4 with numerous silicon inclusions. This nitride, however, has been found to remain amorphous in regions at the center of the implant where the nitrogen concentration exceeds the stoichiometric level of Si3N4. Nitrogen donor formation in the top silicon layer has also been observed.

Growth of Buried Oxide Layers of Silicon‐on‐Insulator Structures by Thermal Oxidation of the Top Silicon Layer

1997 ◽  
Vol 144 (6) ◽  
pp. 2205-2210 ◽  
Author(s):  
E. Schroer ◽  
S. Hopfe ◽  
Q. Y. Tong ◽  
U. Gösele ◽  
W. Skorupa
Keyword(s):  
Thermal Oxidation ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Oxide Layers ◽  
Buried Oxide

Formation of stacking-fault tetrahedra in low defect density oxygen-implanted silicon-on-insulator material

1992 ◽  
Vol 50 (2) ◽  
pp. 1402-1403
Author(s):  
June-Dong Lee ◽  
Stephen Krause ◽  
Peter Roitman
Keyword(s):  
Integrated Circuits ◽  
Defect Density ◽  
Silicon Layer ◽  
Stacking Fault ◽  
Silicon On Insulator ◽  
Threading Dislocations ◽  
Annealing Conditions ◽  
Stacking Fault Tetrahedra ◽  
Higher Temperature ◽  
Defect Densities

Fabrication of integrated circuits on SOI (Silicon-On-Insulator) material is very attractive because it offers high component density, immunity to latch-up and radiation hardness. Among various SOI techniques SIMOX Separation by IMplantation of OXygen) provides the best material, with carrier mobilities and defect densities approaching bulk silicon values, Early SIMOX wafers were implanted at temperatures below 600°C and annealed at high temperature (>1300°C), which gave a high defect density (109cm−2), including threading dislocations and narrow stacking faults (SFs), as shown in Figure 1. Higher temperature (>600°C) implantation of SIMOX reduced defect densities to 106cm-2 with pairs of narrow SFs in the top silicon layer, as shown in Figure 2. This paper describes a further reduction of defect density in SIMOX material through various annealing conditions, which has resulted in a defect density less than 105cm−2. A new formation mechanism for stacking fault tetrahedra is also discussed.Silicon (100) wafers were sequentially implanted (620°C) and annealed (at 1320°C for 5 hours) to doses of 0.5, 0.5, and 0.8×l018cm-2.

A Microscale Piezoresistive Force Sensor for Nanoindentation of Biological Cells and Tissues

2013 ◽  
Author(s):  
Hardik J. Pandya ◽  
Hyun Tae Kim ◽  
Jaydev P. Desai
Keyword(s):  
Silicon Wafer ◽  
Cantilever Beam ◽  
Silicon Film ◽  
Silicon Layer ◽  
Force Sensor ◽  
Silicon On Insulator ◽  
Potential Candidate ◽  
Micro Electro Mechanical Systems ◽  
Silicon Cantilever ◽  
The Cost

We present the design and fabrication of a Micro-Electro-Mechanical Systems based piezoresistive cantilever force sensor as a potential candidate for micro/nano indentation of biological specimens such as cells and tissues. The fabricated force sensor consists of a silicon cantilever beam with a p-type piezoresistor and a cylindrical probing tip made from SU-8 polymer. One of the key features of the sensor is that a standard silicon wafer is used to make silicon-on-insulator (SOI), thereby reducing the cost of fabrication. To make SOI from standard silicon wafer the silicon film was sputtered on an oxidized silicon wafer and annealed at 1050 °C so as to obtain polycrystalline silicon. The sputtered silicon layer was used to fabricate the cantilever beam. The as-deposited and annealed silicon films were experimentally characterized using X-ray diffraction (XRD) and Atomic Force Microscopy (AFM). The annealed silicon film was polycrystalline with a low surface roughness of 3.134 nm (RMS value).

High-Quality SOI by Oxygen Implantation into Silicon

1987 ◽  
Vol 93 ◽  
Author(s):  
A. H. van Ommen ◽  
H. J. Ligthart ◽  
J. Politiek ◽  
M. P. A. Viegers
Keyword(s):  
High Temperature ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
High Dose ◽  
High Temperature Annealing ◽  
High Quality ◽  
Cubic Symmetry ◽  
Buried Oxide ◽  
Simple Cubic ◽  
Precipitate Growth

ABSTRACTHigh quality Silicon-On-Insulator, with a dislocation density lower than 105cm−2, has been formed by high temperature annealing of high-dose oxygen implanted silicon. In the as-implanted state, oxygen was found to form precipitates in the top silicon film. In the upper region these precipitates were found to order into a superlattice of simple cubic symmetry. Near the interface with the buried oxide film the precipitates are larger and no ordering occurs in that region. Contrary to implants without precipitate ordering where dislocations are observed across the entire layer thickness of the top silicon film, dislocations are now only found near the buried oxide. The precipitate ordering appears to prevent the dislocations to climb to the surface. High temperature annealing results in precipitate growth in this region whereas they dissolve elsewhere. These growing precipitates pin the dislocations and elimination of precipitates and dislocations occurs simultaneously, resulting in good quality SOI material.

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

Effect Of Nickel In Large Grain Poly-Si Film Formed By Nickel Induced Lateral Crystallization and New Grain Enhancement Method

2000 ◽  
Vol 609 ◽  
Author(s):  
W.Y. Chan ◽  
A.M. Myasnikov ◽  
M.C. Poon ◽  
C.Y. Yuen ◽  
P. G. Han ◽  
...  
Keyword(s):  
Low Cost ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
3 Dimensional ◽  
Enhancement Method ◽  
Novel Method ◽  
Amorphous Si ◽  
Lateral Crystallization ◽  
Novel Applications ◽  
Soi Substrates

ABSTRACTLarge grain poly-silicon film (poly-Si) with high material quality and uniformity can have numerous novel applications such as providing a low cost alternative to form silicon-on-insulator (SOI) substrates and a breakthrough technology to ultra-dense 3-dimensional multi-layer SOI like devices and circuits. Nickel Induced Lateral Crystallization (NILC) of amorphous Si (a-Si) has been studied intensively, yet the grains are still small (∼ 1 μm). Recently, we have reported a novel method by combining NILC and a new annealing (at above 900 °C) to form poly-Si film with very large grains ranging from 10 μm to 100 μm. The film has good quality and the TFTs formed are highly comparable to SOI TFTs. This work further reports the effect of Ni to the new large-grain poly-Si film.

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