Hydrogen/Deuterium Interaction With CMOS Transistor Device Structure: Sintering Process Studied by Sims

1998 ◽  
Vol 513 ◽  
Author(s):  
P. J. Chen ◽  
R. M. Wallace

ABSTRACTPassivation of the SiO2-Si interface by hydrogen/deuterium in MOS transistors serve to ensure their operating reliability against channel hot carriers. Physical characterization of device sintering process in deuterated forming gas (10%D2:90%N2) is carried out by dynamic SIMS on planar CMOS gate stack structures, in conjunction with device hot carrier electrical testing. It is found that incorporation of deuterium in the doped poly-Si/SiO2/Si interfacial region readily occurs under typical post-metallization sintering conditions, demonstrating that transport of deuterium through CMOS gate is an effective pathway in an encapsulated device structure with silicon nitride sidewalls. The measured Si-D areal densities in the interfacial region depend on gate poly-Si doping type, but in both cases, appear to be sufficient to achieve complete interface Si dangling bond (˜1012 cm−2) passivation for the SiO2-Si system.

1990 ◽  
Vol 37 (3) ◽  
pp. 708-717 ◽  
Author(s):  
M. Bourcerie ◽  
B.S. Doyle ◽  
J.-C. Marchetaux ◽  
J.-C. Soret ◽  
A. Boudou

1998 ◽  
Vol 510 ◽  
Author(s):  
J. Lee ◽  
Z. Chen ◽  
K. Hess ◽  
J.W. Lyding

AbstractIt has been found that deuterium (D) instead of hydrogen (H) can be used to greatly strengthen the resistance of metal oxide semiconductor (MOS) transistors against hot carrier induced degradation. We have applied the new deuterium sintering process to CMOS technology and have obtained significantly improved hot carrier reliability resulting from the isotope effect. We will present a summary of these lifetime improvements from five different transistor structures of five different manufacturers, as well as the physical and electrical characterizations of the deuterium sintering process.


2003 ◽  
Vol 26 (4) ◽  
pp. 197-204
Author(s):  
R. Marrakh ◽  
A. Bouhdada

The hot-carrier injection is observed increasingly to degrade the I–V characteristics with the scaling of MOS transistors. For the lightly doped drain MOS transistor the injection of the hot-carriers, caused by the high electric field in the MOS structure, is localized in the LDD region. The modeling of the drain current in relation to defects due to the hot-carrier injection allows us to investigate the I–V characteristics and the transconductance of devices. Consequently, we can know the amount of the device degradation caused by these defects in order to find technological solutions to optimize reliability.


1988 ◽  
Vol 49 (C4) ◽  
pp. C4-651-C4-655 ◽  
Author(s):  
R. BELLENS ◽  
P. HEREMANS ◽  
G. GROESENEKEN ◽  
H. E. MAES

Author(s):  
Yuk L. Tsang ◽  
Alex VanVianen ◽  
Xiang D. Wang ◽  
N. David Theodore

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.


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