Charge Trapping and Degradation of High Permittivity TiO2 Dielectric Metal-Oxide-Semiconductor Field Effect Transistors

1996 ◽  
Vol 448 ◽  
Author(s):  
Hyeon-Saeg Kim ◽  
S.A. Campbell ◽  
D.C. Gilmer ◽  
D.L. Polla
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Interface States ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Organic Chemical

AbstractSuitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and capacitance-voltage measurements were done on 190Å layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide. Measurements of the high and low frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

Characterization of the Seed SiO2 Layer in Stacked SiO2-Ta2O5 Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
Pradip K. Roy ◽  
Michael A. Laughery ◽  
Carlos M. Chacon ◽  
Ayman M. Kanan ◽  
Thomas Daugherty
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Organic Chemical ◽  
Trap States ◽  
Electrical Measurements ◽  
High Concentrations ◽  
High Dielectric

ABSTRACTA major hurdle in the gate dielectric scaling using conventionally grown SiO2 has been excessive tunneling that occurs in ultra-thin (<25Å) SiO2. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta2O5 interface trap states, and low Silicon interface carrier mobilities. Stacked Ta2O5 gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first SiO2 (8-12Å) layer of the SiO2-Ta2O5 stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness (Tox) of these oxides measured by COS indicates this hydrocarbon layer has no impact on Tox. Stacked Ta2O5 was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick Ta2O5 layer at 480°C, 300mTorr followed by an in-situ 550°C UV-03 anneal to densify the Ta2O5 film and grow an additional 5Å SiO2 layer underneath the first grown SiO2 layer resulting in an effective SiO2 thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown SiO2 layer resulting in an effective SiO2 thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements.

Transmission Electron Microscopy Study of an Epitaxial Gate Oxide on III-N Semiconductor Structures

2004 ◽  
Vol 831 ◽  
Author(s):  
Yoga. N. Saripalli ◽  
X-Q Liu ◽  
D.W. Barlage ◽  
M.A.L. Johnson ◽  
D. Braddock ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Organic Chemical ◽  
High Electron ◽  
Semiconductor Interface ◽  
Transmission Electron

ABSTRACTAn effective gate insulator for compound semiconductors has been a challenging goal for the materials research community for nearly 40 years. Recent developments on the epitaxial deposition of complex gate oxides as gate insulators have shown promise with the demonstration of enhancement mode high electron mobility transistors (e-mode HEMTs). In this work, gate oxide epilayers deposited on III-V semiconductors for field effect transistors (III-V MOSFETs) are examined using transmission electron microscopy (TEM) to identify the structure of the oxide/semiconductor interface. The high resolution images of the cross-sectional structures for the first time reveal a crystalline nature of the interface between the oxide and the III-V semiconductor. The composition of the oxide layers are determined by Z-contrast Electron Energy Loss Spectroscopy (EELS). The surface morphology of the FET structures is investigated by atomic force microscopy (AFM) both before and after gate oxide deposition, and the structural results are related to device DC electrical characteristics. With an underlying GaN/InGaN heterojunction grown by metal-organic chemical vapor deposition (MOCVD) on sapphire, the MOSFET devices exhibit the characteristics of a substantially unpinned interface, including the capacity for significant charge accumulation and transconductance at positive gate voltages.

scholarly journals InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities

Materials ◽  
2018 ◽  
Vol 12 (1) ◽  
pp. 87 ◽  
Author(s):  
Clarissa Convertino ◽  
Cezar Zota ◽  
Heinz Schmid ◽  
Daniele Caimi ◽  
Marilyne Sousa ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Chemical Vapor ◽  
Advanced Technology ◽  
Oxide Semiconductor ◽  
Organic Chemical ◽  
Gate Length ◽  
High Electron ◽  
Monolithically Integrated ◽  
Scanning Transmission ◽  
Technology Nodes

III-V semiconductors are being considered as promising candidates to replace silicon channel for low-power logic and RF applications in advanced technology nodes. InGaAs is particularly suitable as the channel material in n-type metal-oxide-semiconductor field-effect transistors (MOSFETs), due to its high electron mobility. In the present work, we report on InGaAs FinFETs monolithically integrated on silicon substrates. The InGaAs channels are created by metal–organic chemical vapor deposition (MOCVD) epitaxial growth within oxide cavities, a technique referred to as template-assisted selective epitaxy (TASE), which allows for the local integration of different III-V semiconductors on silicon. FinFETs with a gate length down to 20nm are fabricated based on a CMOS-compatible replacement-metal-gate process flow. This includes self-aligned source-drain n+ InGaAs regrown contacts as well as 4 nm source-drain spacers for gate-contacts isolation. The InGaAs material was examined by scanning transmission electron microscopy (STEM) and the epitaxial structures showed good crystal quality. Furthermore, we demonstrate a controlled InGaAs digital etching process to create doped extensions underneath the source-drain spacer regions. We report a device with gate length of 90 nm and fin width of 40 nm showing on-current of 100 µA/µm and subthreshold slope of about 85 mV/dec.

Influence of Epi-Layer Growth Pits on SiC Device Characteristics

2015 ◽  
Vol 821-823 ◽  
pp. 177-180 ◽  
Author(s):  
Chiaki Kudou ◽  
Hirokuni Asamizu ◽  
Kentaro Tamura ◽  
Johji Nishio ◽  
Keiko Masumoto ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Schottky Barrier ◽  
Leakage Current ◽  
Dielectric Breakdown ◽  
Layer Growth ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Schottky Barrier Diodes ◽  
Current Time

Homoepitaxial layers with different growth pit density were grown on 4H-SiC Si-face substrates by changing C/Si ratio, and the influence of the growth pit density on Schottky barrier diodes and metal-oxide-semiconductor capacitors were investigated. Even though there were many growth pits on the epi-layer, growth pit density did not affect the leakage current of Schottky barrier diodes and lifetime of constant current time dependent dielectric breakdown. By analyzing the growth pit shape, the aspect ratio of the growth pit was considered to be the key factor to the leakage current of the Schottky barrier diodes and the lifetime of metal-oxide-semiconductor capacitors.

Quality of Thermally Grown Oxides in 4H-SiC over Nitrogen or Phosphorus Implanted Regions

2000 ◽  
Vol 640 ◽  
Author(s):  
I. A. Khan ◽  
B. Um ◽  
M. Matin ◽  
M. A. Capano ◽  
J. A. Cooper
Keyword(s):  
Field Effect Transistors ◽  
Dielectric Strength ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Gate Electrode ◽  
Nitrogen And Phosphorus ◽  
Thermally Grown Oxides ◽  
Thermal Oxide ◽  
Drain Region

ABSTRACTCurrent SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs) have regions of the gate electrode that overlaps the source/drain contact implant. The source/drain region is electrically isolated from this gate electrode extension by the gate insulator. Typically, the gate insulator is established through a controlled thermal oxidation step. The performance of the electrical isolation between the gate electrode and the source/drain implant region is studied using MOS systems for the nitrogen and phosphorus implant species. The dielectric strength of thermal oxide grown over a phosphorus implanted region is about four times lower than a non-implanted region and about two times lower than the nitrogen implanted region for the same implant and anneal conditions.

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