Characterization of the Seed SiO2 Layer in Stacked SiO2-Ta2O5 Gate Dielectrics

1999 ◽  
Vol 567 ◽  
Author(s):  
Pradip K. Roy ◽  
Michael A. Laughery ◽  
Carlos M. Chacon ◽  
Ayman M. Kanan ◽  
Thomas Daugherty
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Organic Chemical ◽  
Trap States ◽  
Electrical Measurements ◽  
High Concentrations ◽  
High Dielectric

ABSTRACTA major hurdle in the gate dielectric scaling using conventionally grown SiO2 has been excessive tunneling that occurs in ultra-thin (<25Å) SiO2. High dielectric constant materials have high concentrations of bulk fixed charge, unacceptable levels of Si-Ta2O5 interface trap states, and low Silicon interface carrier mobilities. Stacked Ta2O5 gate dielectrics have alleviated these issues with significant improvements in leakage, tunneling, charge trapping behavior, and interface substructure. Transistors fabricated using this stacked gate dielectric exhibit excellent sub threshold, saturation, and drive currents. In this study, we have characterized the first SiO2 (8-12Å) layer of the SiO2-Ta2O5 stack by ThermaWave (TWI 5240SE) absolute ellipsometry (AE) using He-Ne (λ= 630nm) laser light source and by corona oxide semiconductor (COS) non-contact techniques. We have also monitored the kinetics of a thin hydrocarbon layer deposition on top of these films that can be removed by simple heat treatments (250°C - 400°C). Electrical thickness (Tox) of these oxides measured by COS indicates this hydrocarbon layer has no impact on Tox. Stacked Ta2O5 was synthesized by metal organic chemical vapor deposition (MOCVD) of a 50-75Å thick Ta2O5 layer at 480°C, 300mTorr followed by an in-situ 550°C UV-03 anneal to densify the Ta2O5 film and grow an additional 5Å SiO2 layer underneath the first grown SiO2 layer resulting in an effective SiO2 thickness of 25-30Å (process 1). We have done exactly the same deposition schedule after chemically removing the first LP grown SiO2 layer resulting in an effective SiO2 thickness of 15-20Å (process 2). Transistors are now fabricated for our sub-0.16μm CMOS technologies. These stacked films indicated excellent charge trapping (Dit, Vfb, Qtot), leakage and tunneling characteristics from COS electrical measurements.

Charge Trapping and Degradation of High Permittivity TiO2 Dielectric Metal-Oxide-Semiconductor Field Effect Transistors

1996 ◽  
Vol 448 ◽  
Author(s):  
Hyeon-Saeg Kim ◽  
S.A. Campbell ◽  
D.C. Gilmer ◽  
D.L. Polla
Keyword(s):  
Dielectric Breakdown ◽  
Field Effect Transistors ◽  
Tunneling Current ◽  
Chemical Vapor ◽  
Charge Trapping ◽  
Interface States ◽  
Gate Insulator ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Organic Chemical

AbstractSuitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and capacitance-voltage measurements were done on 190Å layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide. Measurements of the high and low frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

Interface Quality and Electrical Performance of Low-Temperature Metal Organic Chemical Vapor Deposition Aluminum Oxide Thin Films for Advanced CMOS Gate Dielectric Applications

2002 ◽  
Vol 745 ◽  
Author(s):  
Spyridon Skordas ◽  
Filippos Papadatos ◽  
Steven Consiglio ◽  
Eric Eisenbraun ◽  
Alain Kaloyeros
Keyword(s):  
Dielectric Constant ◽  
Leakage Current ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Organic Chemical ◽  
Si Substrates ◽  
Annealing Conditions ◽  
Metal Organic

ABSTRACTIn this work, the electrical performance and interfacial characteristics of MOCVD-grown Al2O3 films are evaluated. Electrical characteristics (dielectric constant, leakage current) of as-deposited and annealed capacitor metal-oxide-semiconductor (MOS) stacks were determined using capacitance-voltage (C-V) and current-voltage (I-V) measurements. It was observed that the electrical properties were dependent upon specific annealing conditions, with an anneal in O2 followed by forming gas being superior with respect to leakage current, resulting in leakage characteristics superior to those of SiO2. All annealing conditions evaluated led to an increase in dielectric constant from 6.5 to 9.0–9.8. Also, Al2O3 growth and interfacial oxide growth characteristics on oxynitride/Si and Si substrates were evaluated and compared using spectroscopic ellipsometry. A parasitic oxide layer was observed to form on silicon during the initial stages of MOCVD Al2O3 growth, while a thin oxynitride layer deposited on Si prevented the growth of interfacial oxide.

Study of Germanium Diffusion in HfO2 Gate Dielectric of MOS Device Application

2004 ◽  
Vol 829 ◽  
Author(s):  
Qingchun Zhang ◽  
Nan Wu ◽  
L.K. Bera ◽  
Chunxiang Zhu
Keyword(s):  
Vapor Deposition ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Chemical Vapor ◽  
Device Fabrication ◽  
Organic Chemical ◽  
Vapor Deposition Technique ◽  
Metal Organic ◽  
Organic Chemical Vapor Deposition ◽  
Mos Device

ABSTRACTSignificant germanium incorporation into HfO2 gate dielectrics has been found after thermal annealing in germanium MOS device. The dependences of germanium incorporation in HfO2 with dielectric deposition method, annealing temperature and annealing ambient were extensively studied by means of physical analytical methods such as SIMS and XPS. MOCVD (metal organic chemical vapor deposition) technique shows stronger germanium incorporation than PVD (physics vapor deposition) while surface nitridation of germanium can effectively suppress the Ge-incorporation. In addition, the results indicate that a thermal budget higher than 500°C in device fabrication results in apparent Ge out-diffusion. And the germanium out-diffusion is found to be enhanced under oxygen environment.

NANOSTRUCTURAL PROPERTIES OF La2O3/HfO2 GATE DIELECTRICS

2012 ◽  
Vol 26 (14) ◽  
pp. 1250080 ◽  
Author(s):  
A. BAHARI ◽  
A. RAMZANNEJAD
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Wide Band ◽  
Amorphous Structure ◽  
Boron Diffusion ◽  
Wide Band Gap ◽  
Good Thermal Stability ◽  
Force Microscopy ◽  
Alternative Material ◽  
High Dielectric

There are some issues such as tunneling, leakage currents and boron diffusion through the ultra thin SiO 2 which are threatening ultra thin SiO 2 dielectric as a good gate dielectric. A very obvious alternative material is HfO 2, due to its high dielectric constant, wide band gap and good thermal stability on silicon substrate. We have thus demonstrated a number of processes to synthesize La 2 O 3/ HfO 2 and studied its nano structural properties with using X-ray diffraction (XRD), Fourier transform infrared spectroscopy (FTIR), scanning electron microscopy (SEM) and atomic force microscopy (AFM) techniques. The obtained results show that La 2 O 3/ HfO 2 (at 500°C with amorphous structure) can be introduced as a good gate dielectric for the future of complementary metal insulator semiconductor (CMIS) device.

Charge trapping behaviour in deposited and grown thin metal-oxide-semiconductor gate dielectrics

1997 ◽  
Vol 296 (1-2) ◽  
pp. 37-40 ◽  
Author(s):  
V. Ramgopal Rao ◽  
W. Hansch ◽  
H. Baumgärtner ◽  
I. Eisele ◽  
D.K. Sharma ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Metal Oxide Semiconductor ◽  
Thin Metal ◽  
Oxide Semiconductor

High Quality Ultrathin Gate Dielectrics Prepared by In-Situ RTP

1995 ◽  
Vol 387 ◽  
Author(s):  
L. K. Han ◽  
M. Bhat ◽  
J. Yan ◽  
D. Wristers ◽  
D. L. Kwong
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
High Quality ◽  
Hot Carrier ◽  
Thermal Oxide ◽  
State Generation

AbstractThis paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

scholarly journals Role of hydrogen in volatile behaviour of defects in SiO 2 -based electronic devices

2016 ◽  
Vol 472 (2190) ◽  
pp. 20160009 ◽  
Author(s):  
Yannick Wimmer ◽  
Al-Moatasem El-Sayed ◽  
Wolfgang Gös ◽  
Tibor Grasser ◽  
Alexander L. Shluger
Keyword(s):  
Ab Initio ◽  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Electronic Devices ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Gate Oxides ◽  
And Performance ◽  
Silicon Based

Charge capture and emission by point defects in gate oxides of metal–oxide–semiconductor field-effect transistors (MOSFETs) strongly affect reliability and performance of electronic devices. Recent advances in experimental techniques used for probing defect properties have led to new insights into their characteristics. In particular, these experimental data show a repeated dis- and reappearance (the so-called volatility ) of the defect-related signals. We use multiscale modelling to explain the charge capture and emission as well as defect volatility in amorphous SiO 2 gate dielectrics. We first briefly discuss the recent experimental results and use a multiphonon charge capture model to describe the charge-trapping behaviour of defects in silicon-based MOSFETs. We then link this model to ab initio calculations that investigate the three most promising defect candidates. Statistical distributions of defect characteristics obtained from ab initio calculations in amorphous SiO 2 are compared with the experimentally measured statistical properties of charge traps. This allows us to suggest an atomistic mechanism to explain the experimentally observed volatile behaviour of defects. We conclude that the hydroxyl-E′ centre is a promising candidate to explain all the observed features, including defect volatility.

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