The Poly-Si Tfts Fabricated by Novel Oxidation Method with Intermediate Oxide

1996 ◽  
Vol 424 ◽  
Author(s):  
C-M Park ◽  
J-S Yoo ◽  
B-H Min ◽  
M-K Han
Keyword(s):  
Surface Roughness ◽  
Oxide Layer ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Dielectric Strength ◽  
Device Performance ◽  
Electrical Parameters ◽  
Oxidation Method ◽  
Electrical Stress ◽  
Intermediate Oxide

AbstractWe have fabricated a poly-Si TFT using a novel oxidation method, which improves the surface roughness at the interface between the poly-Si layer and the gate oxide layer. Compared with the poly-Si TFTs fabricated by the conventional oxidation method, the proposed poly-Si TFT exhibits the remarkable enhancement of the electrical parameters, such as the subthreshold swing and the threshold voltage. It is observed that the proposed poly-Si TFT has a higher dielectric strength and the device characteristics are not degraded significantly after an electrical stress. The improvement of the surface roughness at oxide/poly-Si interface is found to be critical to enhance the device performance.

Improved Surface Roughness at Poly-Oxide/Poly-Si Interface by a Novel Oxidation Method

1994 ◽  
Vol 343 ◽  
Author(s):  
M.C. Jun ◽  
J.W. Kim ◽  
K.B. Kim ◽  
B.C. Ahn ◽  
M.K. Han
Keyword(s):  
Electron Microscopy ◽  
Surface Roughness ◽  
Oxide Layer ◽  
The Novel ◽  
Oxidation Method ◽  
Force Microscopy ◽  
Silicon Source ◽  
Atomic Force ◽  
Transmission Electron ◽  
Intermediate Oxide

ABSTRACTWe present a novel oxidation method to improve the surface roughness at the poly-oxide/poly-Si interface. Instead of directly oxidizing the poly-Si to the desired thickness of the SiO2, a thin oxide layer is thermally grown on the poly-Si layer and then an a-Si layer is deposited on the top of the oxide layer. The a-Si layer is used as a silicon-source during next step of oxidation. The a-Si layer is fully oxidized until the poly-oxide/poly-Si interface advances below the initial interface. For comparison, the poly-oxide/poly-Si interface is also obtained by the conventional oxidation method. The surface roughness at the interface is investigated using transmission electron microscopy (TEM) and atomic force microscopy (AFM). For the novel oxidation method with the 50 Å thick intermediate oxide, the rms surface roughness at the poly-oxide/poly-Si interface is 30 Å, whereas that is 120 Å for the conventional method.

Performance of Poly-Si Tfts with Double Gate Oxide Layers

1996 ◽  
Vol 424 ◽  
Author(s):  
Byung-Hyuk Min ◽  
Cheol-Min Park ◽  
Jae-Hong Jun ◽  
Byung-Sung Bae ◽  
Min-Koo Han
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Gate Insulator ◽  
Double Gate ◽  
Electrical Parameters ◽  
Electrical Field ◽  
Oxide Layers ◽  
Oxide Breakdown ◽  
Electrical Stress ◽  
Low Threshold

AbstractWe have fabricated a poly-Si TFT with double gate insulator composed of ECR oxide and APCVD oxide to improved the performance of poly-Si TFTs. The poly-Si TFT with double gate oxide exhibits the remarkable enhancement of the electrical parameters compared with the conventional poly-Si TFTs which has APCVD gate oxide, such as improvement of the subthreshold swing and the low threshold voltage. The proposed poly-Si TFT has a higher oxide breakdown electrical field and the device characteristics are not degraded significantly after an electrical stress. It is found that the ECR oxide plays a key role to improve the device performances and prevent the poly-Si TFTs from degradation due to the electrical stress.

Improved Device Performance of In0.5Ga0.5P/In0.22Ga0.78As/GaAs MOS p-HEMT using a Selective Liquid Phase Oxidation

2002 ◽  
Vol 744 ◽  
Author(s):  
I-H Kang ◽  
J-W Lee ◽  
S-J Kang ◽  
S-J Jo ◽  
S-K In ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Oxide Layer ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Liquid Phase Oxidation ◽  
Device Performance ◽  
Gate Oxide Thickness ◽  
Phase Oxidation ◽  
Rf Performances

ABSTRACTThe DC and RF characteristics of In0.5Ga0.5P/In0.22Ga0.78As/GaAs MOS p-HEMTs with different gate oxide thickness were investigated and compared with those of Schottky-gate p-HEMT without the gate oxide layer. The oxide layer was implemented by using a liquid phase oxidation technique. It was found that transconductance (gm), threshold voltage and breakdown voltage characteristics of MOS p-HEMTs depended strongly on the gate oxide thickness. The MOS p-HEMTs showed superior DC and RF performances compared with those of GaAs-based MOSFET having oxide/n-GaAs or oxide/InGaAs interface.

Hydrogen Concentration Analysis in Pecvd and Rtcvd Silicon Nitride Thin Films and It's Impact on Device Performance

2001 ◽  
Vol 664 ◽  
Author(s):  
C. Y. Wang ◽  
E. H. Lim ◽  
H. Liu ◽  
J. L. Sudijono ◽  
T. C. Ang ◽  
...  
Keyword(s):  
Chemical Vapor Deposition ◽  
Threshold Voltage ◽  
Vapor Deposition ◽  
Gas Flow ◽  
Chemical Vapor ◽  
Gate Oxide ◽  
Nitride Film ◽  
Device Performance ◽  
Gas Flow Ratio ◽  
The Impact

ABSTRACTIn this paper the impact of the ESL (Etch Stop layer) nitride on the device performance especially the threshold voltage (Vt) has been studied. From SIMS analysis, it is found that different nitride gives different H concentration, [H] in the Gate oxide area, the higher [H] in the nitride film, the higher H in the Gate Oxide area and the lower the threshold voltage. It is also found that using TiSi instead of CoSi can help to stop the H from diffusing into Gate Oxide/channel area, resulting in a smaller threshold voltage drift for the device employed TiSi. Study to control the [H] in the nitride film is also carried out. In this paper, RBS, HFS and FTIR are used to analyze the composition changes of the SiN films prepared using Plasma enhanced Chemical Vapor deposition (PECVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) with different process parameters. Gas flow ratio, RF power and temperature are found to be the key factors that affect the composition and the H concentration in the film. It is found that the nearer the SiN composition to stoichiometric Si3N4, the lower the [H] in SiN film because there is no excess silicon or nitrogen to be bonded with H. However the lowest [H] in the SiN film is limited by temperature. The higher the process temperature the lower the [H] can be obtained in the SiN film and the nearer the composition to stoichiometric Si3N4.

Impact of Carbon on Threshold Voltage Shift in MOSFET Studied by 3D Atom Probe Tomography

2017 ◽  
Author(s):  
Ju-Heon Kim ◽  
Euna Ok ◽  
Hyunmi Sim ◽  
Dongkeun Na ◽  
Ho Seok Song ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Atom Probe Tomography ◽  
Analytical Techniques ◽  
Gate Oxide ◽  
Atom Probe ◽  
Single Atom ◽  
Device Performance ◽  
Si Substrate ◽  
Threshold Voltage Shift ◽  
Voltage Shift

Abstract In this paper, impact of carbon on threshold voltage in MOSFET-based device is studied by 3D-atom probe tomography (APT). Carbon is one of most difficult contaminants incorporated from fab-environment to be detected by typical analytical techniques such as TEM-EDS or SIMS. Here, we successfully demonstrated the detection of carbon segregated at gate oxide/Si substrate interface using 3D-APT with single-atom sensitivity and sub-nanometer spatial resolution. It was found that the carbon contaminants have significant effect on the threshold voltage shift (ΔVth), in which ΔVth increases slightly with increasing carbon concentration. The deterioration of device performance is explained by means of which the positively ionized carbons at the interface acting as additional positive charges affecting the inversion to n-channel.

Combined Metallurgical and Ceramic Coating in the Development of Tubular Ozone Generators

1998 ◽  
Author(s):  
R. Gadow ◽  
A. Killinger ◽  
A. Voss ◽  
C. Friedrich
Keyword(s):  
Surface Roughness ◽  
Oxide Layer ◽  
Borosilicate Glass ◽  
Electrode Surface ◽  
Ceramic Coating ◽  
Dielectric Strength ◽  
Production Costs ◽  
Multilayer Coatings ◽  
Oxide Ceramic ◽  
Tremendous Impact

Abstract This article discusses the development of a novel efficient ozonizer tube which cuts down the production costs and thus causes ozone to be an economically competitive alternative in comparison to traditionally used chlorine compounds. It describes the principle of ozone generation, provides information on improved ozonizer tubes, and presents the criteria for selecting thermal spray powders. The article investigates several types of thermal sprayed multilayer coatings, consisting of an Al/Si intermetallic interlayer and an oxide ceramic top coating on a borosilicate glass. It was found that the structural constitution namely, porosity and electrode surface roughness of the oxide layer, has a tremendous impact on the dielectric strength of the composite.

Nitric Acid Oxidation Method to Form a Gate Oxide Layer in Sub-Micrometer TFT

2019 ◽  
Vol 35 (4) ◽  
pp. 217-227 ◽  
Author(s):  
Taketoshi Matsumoto ◽  
Yasushi Kubota ◽  
Shigeki Imai ◽  
Hikaru Kobayashi
Keyword(s):  
Nitric Acid ◽  
Oxide Layer ◽  
Gate Oxide ◽  
Acid Oxidation ◽  
Oxidation Method ◽  
Nitric Acid Oxidation

scholarly journals Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

2020 ◽  
Vol 9 (3) ◽  
pp. 1673-1676
Keyword(s):  
Oxide Layer ◽  
Threshold Voltage ◽  
Oxide Thickness ◽  
Vital Role ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Fully Depleted ◽  
Parasitic Parameter

This article is discussing about threshold voltage roll off effect in Ultra Thin Fully Depleted Silicon on Insulator MOSFET. The device performance is improved due to the reduction in threshold voltage roll off. The thickness of oxide layer is optimized to 2nm which also have a vital role in improvement of device’s throughput. The effect of oxide thickness on parasitic parameter also discussed. Device conductance and transconductance also take in account on simulating the ultra thin fully depleted SOIMOSFET

Semi Analytical Modelling for Drain-Induced Barrier Lowering Reduction in Dual-Metal Gate all Around FET

2021 ◽  
Author(s):  
Amit Kumar ◽  
Anil Kumar Rajput ◽  
Manisha Pattanaik ◽  
Pankaj Srivast
Keyword(s):  
Threshold Voltage ◽  
Gate Oxide ◽  
Analytical Modelling ◽  
Device Performance ◽  
Oxide Material ◽  
Metal Gate ◽  
Drain Region ◽  
Dual Metal ◽  
Nitride Oxide ◽  
Potential Threshold

Abstract In the research paper, the semi-analytical modelling is done for low drain-induced barrier lowering (DIBL) dual-metal gate all around FET (DM GAAFET). Vacuum and silicon nitride are considered in the act of the gate oxide material near drain region for dual-metal vacuum oxide gate all around FET (DM-VO GAAFET) and dual-metal nitride oxide gate all around FET (DM-NO GAAFET) respectively, in which surface potential, threshold voltage, and DIBL are modelled for both the devices. The proposed models are validated by comparing DM-NO GAAFET with DM-VO GAAFET. DM-NO GAAFET shows the better device performance than DM-VO GAAFET as the threshold voltage increased by 10% and DIBL decreased by 50% in simulated as well as analytical results. The obtained results are having very close agreement with simulated results for both the GAAFETs.

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