Degradation Phenomena of low-temp. poly-Si TFT's Under Electrical Stress Before and After Hydrogenation

1994 ◽  
Vol 345 ◽  
Author(s):  
Y. S. Kim ◽  
K. Y. Choi ◽  
M. C. Jun ◽  
M. K. Han
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Degradation Mechanism ◽  
Charge Trapping ◽  
Gate Bias ◽  
Bias Stress ◽  
Electrical Stress ◽  
Before And After ◽  
Drain Bias ◽  
Hydrogenation Time

AbstractThe degradation mechanism in hydrogen passivated and as-fabricated poly-Si TFT's are investigated under the various electrical stress conditions. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which was stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

scholarly journals Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Single Layer ◽  
Charge Trapping ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Electrical Stability ◽  
Bias Stress

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

scholarly journals Impact of the Al Mole Fraction in the Bulk- and Surface-State Induced Instability of AlGaN/GaN HEMTs

2012 ◽  
Vol 1432 ◽  
Author(s):  
S. DasGupta ◽  
M. Sun ◽  
A. Armstrong ◽  
R. Kaplar ◽  
M. Marinella ◽  
...  
Keyword(s):  
Mole Fraction ◽  
Monochromatic Light ◽  
Charge Trapping ◽  
Gate Bias ◽  
Bias Stress ◽  
Algan Barrier ◽  
Deep State ◽  
Drain Bias ◽  
Gan Hemts ◽  
The Impact

ABSTRACTCharge trapping and slow (10 s to > 1000 s) detrapping in AlGaN/GaN HEMTs designed for high breakdown voltage (> 1500 V) are studied to identify the impact of Al molefraction and passivation on trapping. Two different trapping components, TG1 (Ea = 0.62 eV) and TG2 (with negligible temperature dependence) in AlGaN dominate under gate bias stress in the off-state. Al0.15Ga0.85N shows much more vulnerability to trapping under gate stress in the absence of passivation than does AlGaN with a higher Al mole fraction. Under large drain bias, trapping is dominated by a much deeper trap TD. Detrapping under illumination by monochromatic light shows TD to have Ea ≈ 1.65 eV in Al0.26Ga0.74N and Ea ≈ 1.85 eV in Al0.15Ga0.85N. This is consistent with a transition from a deep state (Ec - 2.0 eV) in the AlGaN barrier to the 2DEG.

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress

Degradation behavior and degradation mechanism of bridged-grain polycrystalline silicon thin film transistors under AC gate bias stress

2017 ◽  
Vol 32 (2) ◽  
pp. 91-96
Author(s):  
张猛 ZHANG Meng ◽  
夏之荷 XIA Zhi-he ◽  
周玮 ZHOU Wei ◽  
陈荣盛 CHEN Rong-sheng ◽  
王文 WONG Man ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Degradation Mechanism ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Gate Bias Stress

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

High Quality Ultrathin Gate Dielectrics Prepared by In-Situ RTP

1995 ◽  
Vol 387 ◽  
Author(s):  
L. K. Han ◽  
M. Bhat ◽  
J. Yan ◽  
D. Wristers ◽  
D. L. Kwong
Keyword(s):  
Gate Dielectric ◽  
Defect Density ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Interface State ◽  
High Quality ◽  
Hot Carrier ◽  
Thermal Oxide ◽  
State Generation

AbstractThis paper reports on the formation of high quality ultrathin oxynitride gate dielectric by in-situ rapid thermal multiprocessing. Four such gate dielectrics are discussed here; (i) in-situ NO-annealed SiO2, (ii) N2O- or NO- or O2-grown bottom oxide/RTCVD SiO2/thermal oxide, (iii) N2O-grown bottom oxide/Si3N4/N2O-oxide (ONO) and (iv) N2O-grown bottom oxide/RTCVD SiO2/N2O-oxide. Results show that capacitors with NO-based oxynitride gate dielectrics, stacked oxynitride gate dielectrics with varying quality of bottom oxide (O2/N2O/NO), and the ONO structures show high endurance to interface degradation, low defect-density and high charge-to-breakdown compared to thermal oxide. The N2O-last reoxidation step used in the stacked dielectrics and ONO structures is seen to suppress charge trapping and interface state generation under Fowler-Nordheim injection. The stacked oxynitride gate dielectrics also show excellent MOSFET performance in terms of transconductance and mobility. While the current drivability and mobilities are found to be comparable to thermal oxide for N-channel MOSFET's, the hot-carrier immunity of N-channel MOSFET's with the N2O-oxide/CVD-SiO2/N2O-oxide gate dielectrics is found to be significantly enhanced over that of conventional thermal oxide.

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