65.2:Invited Paper: Bias-Stress-Induced Charge Trapping in Flexible Polymer Gate Dielectrics in Organic TFTs

2015 ◽  
Vol 46 (1) ◽  
pp. 966-968 ◽  
Author(s):  
Boseok Kang ◽  
Hyun Ho Choi ◽  
Kilwon Cho
Keyword(s):  
Gate Dielectrics ◽  
Charge Trapping ◽  
Bias Stress ◽  
Flexible Polymer ◽  
Induced Charge

scholarly journals Electrical Characteristics and Stability Improvement of Top-Gate In-Ga-Zn-O Thin-Film Transistors with Al2O3/TEOS Oxide Gate Dielectrics

Coatings ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 1146
Author(s):  
Yih-Shing Lee ◽  
Yu-Hsin Wang ◽  
Tsung-Cheng Tien ◽  
Tsung-Eong Hsieh ◽  
Chun-Hung Lai
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Single Layer ◽  
Charge Trapping ◽  
Indium Gallium Zinc Oxide ◽  
Electrical Characteristics ◽  
Electrical Stability ◽  
Bias Stress

In this work, two stacked gate dielectrics of Al2O3/tetraethyl-orthosilicate (TEOS) oxide were deposited by using the equivalent capacitance with 100-nm thick TEOS oxide on the patterned InGaZnO layers to evaluate the electrical characteristics and stability improvement of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) devices, including positive bias stress (PBS) and negative bias stress (NBS) tests. Three different kinds of gate dielectrics (Al2O3, TEOS, Al2O3/TEOS) were used to fabricate four types of devices, differing by the gate dielectric, as well as its thickness. As the Al2O3 thickness of Al2O3/TEOS oxide dielectric stacks increased, both the on-current and off-current decreased, and the transfer curves shifted to larger voltages. The lowest ∆Vth of 0.68 V and ∆S.S. of −0.03 V/decade from hysteresis characteristics indicate that the increase of interface traps and charge trapping between the IGZO channel and gate dielectrics is effectively inhibited by using two stacked dielectrics with 10-nm thick Al2O3 and 96-nm thick TEOS oxide. The lowest ∆Vth and ∆S.S. values of a-IGZO TFTs with 10-nm thick Al2O3 and 96-nm thick TEOS oxide gate dielectrics according to the PBS and NBS tests were shown to have the best electrical stability in comparison to those with the Al2O3 or TEOS oxide single-layer dielectrics.

Degradation Phenomena of low-temp. poly-Si TFT's Under Electrical Stress Before and After Hydrogenation

1994 ◽  
Vol 345 ◽  
Author(s):  
Y. S. Kim ◽  
K. Y. Choi ◽  
M. C. Jun ◽  
M. K. Han
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Degradation Mechanism ◽  
Charge Trapping ◽  
Gate Bias ◽  
Bias Stress ◽  
Electrical Stress ◽  
Before And After ◽  
Drain Bias ◽  
Hydrogenation Time

AbstractThe degradation mechanism in hydrogen passivated and as-fabricated poly-Si TFT's are investigated under the various electrical stress conditions. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which was stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

Charge trapping and annealing in high-/spl kappa/ gate dielectrics

2004 ◽  
Vol 51 (6) ◽  
pp. 3143-3149 ◽  
Author(s):  
J.A. Felix ◽  
M.R. Shaneyfelt ◽  
D.M. Fleetwood ◽  
J.R. Schwank ◽  
P.E. Dodd ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Charge Trapping

Anomalous Positive Bias Stress Instability in MoS2 Transistors With High-Hydrogen-Concentration SiO2 Gate Dielectrics

2019 ◽  
Vol 40 (2) ◽  
pp. 232-235 ◽  
Author(s):  
Guanhua Yang ◽  
Xichen Chuai ◽  
Jiebin Niu ◽  
Jiawei Wang ◽  
Xuewen Shi ◽  
...  
Keyword(s):  
Hydrogen Concentration ◽  
Gate Dielectrics ◽  
Positive Bias ◽  
High Hydrogen ◽  
Bias Stress

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress
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