scholarly journals Impact of the Al Mole Fraction in the Bulk- and Surface-State Induced Instability of AlGaN/GaN HEMTs

2012 ◽  
Vol 1432 ◽  
Author(s):  
S. DasGupta ◽  
M. Sun ◽  
A. Armstrong ◽  
R. Kaplar ◽  
M. Marinella ◽  
...  
Keyword(s):  
Mole Fraction ◽  
Monochromatic Light ◽  
Charge Trapping ◽  
Gate Bias ◽  
Bias Stress ◽  
Algan Barrier ◽  
Deep State ◽  
Drain Bias ◽  
Gan Hemts ◽  
The Impact

ABSTRACTCharge trapping and slow (10 s to > 1000 s) detrapping in AlGaN/GaN HEMTs designed for high breakdown voltage (> 1500 V) are studied to identify the impact of Al molefraction and passivation on trapping. Two different trapping components, TG1 (Ea = 0.62 eV) and TG2 (with negligible temperature dependence) in AlGaN dominate under gate bias stress in the off-state. Al0.15Ga0.85N shows much more vulnerability to trapping under gate stress in the absence of passivation than does AlGaN with a higher Al mole fraction. Under large drain bias, trapping is dominated by a much deeper trap TD. Detrapping under illumination by monochromatic light shows TD to have Ea ≈ 1.65 eV in Al0.26Ga0.74N and Ea ≈ 1.85 eV in Al0.15Ga0.85N. This is consistent with a transition from a deep state (Ec - 2.0 eV) in the AlGaN barrier to the 2DEG.

Degradation Phenomena of low-temp. poly-Si TFT's Under Electrical Stress Before and After Hydrogenation

1994 ◽  
Vol 345 ◽  
Author(s):  
Y. S. Kim ◽  
K. Y. Choi ◽  
M. C. Jun ◽  
M. K. Han
Keyword(s):  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Degradation Mechanism ◽  
Charge Trapping ◽  
Gate Bias ◽  
Bias Stress ◽  
Electrical Stress ◽  
Before And After ◽  
Drain Bias ◽  
Hydrogenation Time

AbstractThe degradation mechanism in hydrogen passivated and as-fabricated poly-Si TFT's are investigated under the various electrical stress conditions. It is observed that the charge trapping in the gate dielectric is the dominant degradation mechanism in poly-Si TFT's which was stressed by the gate bias alone while the creation of defects in the poly-Si film is prevalent in gate and drain bias stressed devices. The degradation due to the gate bias stress is dramatically reduced with hydrogenation time while the degradation due to the gate and drain bias stress is increased a little. From the experimental results, it is considered that hydrogenation suppress the charge trapping at gate dielectrics as well as improve the characteristics of poly-Si TFT's.

Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor

2011 ◽  
Vol 99 (2) ◽  
pp. 022104 ◽  
Author(s):  
Te-Chih Chen ◽  
Ting-Chang Chang ◽  
Tien-Yu Hsieh ◽  
Wei-Siang Lu ◽  
Fu-Yen Jian ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Charge Trapping ◽  
Gate Bias ◽  
Degradation Behavior ◽  
Bias Stress ◽  
Trapping Effect ◽  
Gate Bias Stress

The Effect of Forward Gate Bias Stress on the Noise Performance of Mesa Isolated GaN HEMTs

2015 ◽  
Vol 15 (1) ◽  
pp. 40-46 ◽  
Author(s):  
Olle Axelsson ◽  
Mattias Thorsell ◽  
Kristoffer Andersson ◽  
Niklas Rorsman
Keyword(s):  
Gate Bias ◽  
Noise Performance ◽  
Bias Stress ◽  
Gan Hemts ◽  
Gate Bias Stress

The Impact of Fermi Pinning on Thermal Properties of the Instabilities in ZnO TFTs

2006 ◽  
Vol 957 ◽  
Author(s):  
R.B.M. Cross ◽  
M. M. De Souza
Keyword(s):  
Charge Trapping ◽  
Drain Current ◽  
Conduction Band Edge ◽  
Interfacial Region ◽  
Gate Bias ◽  
Trap States ◽  
High Concentration ◽  
Channel Mobility ◽  
High Level ◽  
The Impact

ABSTRACTIn this paper we describe gate bias and temperature induced device instabilities of inverted-staggered ZnO-TFTs. It is shown that low positive and negative gate bias results in the transfer characteristics shifting in a positive and negative direction respectively. It is suggested that this is a consequence of temporary charge trapping at or close to the channel/insulator interface. The degradation of device parameters such as the threshold voltage, subthreshold slope and effective channel mobility is demonstrated at elevated measurement temperatures, suggesting the generation of defects and/or trap states in the interfacial region. In addition, it is postulated from the extracted activation energy of the drain current that the Fermi-level is pinned during the operation of the devices due to the high level of states close to the conduction band edge. These results highlight the relatively ease with which defects could be created at the interface, indicating a high concentration of weak or strained bonds. Both charge trapping and defect creation-induced instabilities appear to be reversible, as all devices regain their original characteristics after a period of relaxation at room temperature.

Sign in / Sign up

Export Citation Format

Share Document