Rapid Thermal Processing of Shallow Junctions Using Epitaxial CoSi2 as a Doping Source

1994 ◽  
Vol 342 ◽  
Author(s):  
Erin C. Jones ◽  
Shinichi Ogawa ◽  
Paul Ameika ◽  
M. Lawrence A. Dass ◽  
David B. Fraser ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Ion Implantation ◽  
Leakage Current ◽  
Thermal Processing ◽  
Polycrystalline Material ◽  
Metal Layer ◽  
Rapid Thermal Processing ◽  
Shallow Junctions ◽  
Total Leakage ◽  
Current Densities

ABSTRACTThe electrical properties of shallow P+/N junctions formed by boron outdiffusion from polycrystalline and epitaxial CoSi2 contacts are discussed. The CoSi2 contacts are grown on (100) Si from a sputtered metal layer by rapid thermal annealing (RTA) at 900°C in forming gas. The epitaxial CoSi2 (epi-CoSi2) is made from layers of 15 nm Co / 2 nm Ti, and the polycrystalline material (poly-CoSi2) is made from a 15 nm Co layer with no Ti. Dopant is introduced by ion implantation into the silicide and the P+/N junctions are formed by a second RTA step. Junctions are found to have total leakage current densities as low as 4 nA/cm2 for poly-CoSi2 and 12 nA/cm2 for epi-CoSi2 at -5V and metallurgical junction depths of 60 nm beyond silicide/Si interface after 700-800°C annealing.

Electrical properties of thin SiO2 films nitrided in N2O by rapid thermal processing

1992 ◽  
Vol 19 (1-4) ◽  
pp. 657-660
Author(s):  
M. Severi ◽  
G. Mattei ◽  
L. Dori ◽  
P. Maccagnani ◽  
G.L. Baldini ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Sio2 Films

Ion Implantation-Induced Defects and the Influence of Titanium Silicidation

1998 ◽  
Vol 510 ◽  
Author(s):  
D.Z. Chi ◽  
S. Ashok ◽  
D. Theodore
Keyword(s):  
Ion Implantation ◽  
Thermal Processing ◽  
Thermal Evolution ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Thermal Signature ◽  
P Type ◽  
Induced Defects

AbstractThermal evolution of ion implantation-induced defects and the influence of concurrent titanium silicidation in pre-amorphized p-type Si (implanted with 25 KeV, 1016 cm2Si+) under rapid thermal processing (RTP) have been investigated. Presence of implantation-induced electrically active defects has been confirmed by current-voltage (IV) and deep level transient spectroscopy (DLTS) measurements. DLTS characterization results show that the evolution of electrically active defects in the Si implanted samples under RTP depend critically on the RTP temperature: Hole traps HI (0.33 eV) and H4 (0.47 eV) appear after the highest temperature (950 °C) anneal, while a single trap H3 (0.26 eV) shows up at lower anneal temperatures (≤ 900 °C). The thermal signature of H4 defect is very similar to that of the iron interstitial while those of HI and H3 levels appear to originate from some interstitial-related defects, possibly complexes. A most interesting finding is that the above interstitial related defects can be eliminated completely with Ti silicidation, apparently a result of vacancy injection. However the silicidation process itself introduces a new H2 (0.30 eV) level, albeit at much lower concentration. This same H2 level is also seen in unimplanted samples under RTP. The paper will present details of defect evolution under various conditions of RTP for samples with and without the self-implantation and silicidation.

Nitrogen-Atom Bonding at Sio2/SI Interfaces in Metalinsulator-Semiconductor (MIS) Stacked Gates Made by Integration of Plasma Assisted Oxidation-Deposition and Rapid Thermal Processing

1993 ◽  
Vol 303 ◽  
Author(s):  
Y. Ma ◽  
T. YAsuda ◽  
G. Lucovsky
Keyword(s):  
Electrical Properties ◽  
Thermal Processing ◽  
High Frequency ◽  
Electron Spectroscopy ◽  
Auger Electron ◽  
Rapid Thermal Processing ◽  
Atom Concentration ◽  
Bonding Structure ◽  
Static Capacitance ◽  
Capacitance Voltage

ABSTRACTSiO2 thin films were deposited by remote PECVD on Si surfaces exposed to species generated in O2/N2 and O2/NH3 plasmas. The surface chemistry was studied by Auger Electron Spectroscopy, AES, and the electrical properties of the SiO2/Si interface by high frequency and quasi-static Capacitance-Voltage, C-V, measurements. The AES results showed that Ccontamination was removed by exposure to both plasma-excited gas mixtures, but that N-atoms were incorporated into the SiO2 film, and Si-N bonds were formed at the SiO2/Si interface. C-V measurements indicated that the Si-N bonding structure, rather than the N-atom concentration, is critical in determining the interface electrical properties. The effects of Rapid Thermal Annealing, RTA, on the electrical properties of these SiO2/Si interfaces were also studied.

The Effect of Ion Implantation on ISFET-Sensing Membrane

2010 ◽  
Vol 93-94 ◽  
pp. 133-136
Author(s):  
Rungtawee Piyananjaratsri ◽  
Win Bunjongpru ◽  
E. Chaowicharat ◽  
O. Trithaveesak ◽  
K. Saeteaw ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Ion Implantation ◽  
Leakage Current ◽  
Membrane Area ◽  
Sensing Membrane

This research studied the effect of ion implantation on electrical properties of ISFETs. In the experiments the sensing membrane area were implanted with 3 types of ions (Boron(B), Phosphorus(P), and Arsenic(As)). After the implantation without annealing, the IV-characteristics of Source/Drain (P-N junction) of ISFET were performed and compared with the behaviour before implantation. In addition, the response to acid-alkaline (sensitivity) of ISFET were also studied. From the results the leakage current of source-drain, P-N junction like, decreases significantly after the implantation. However, this process damaged the devices so that the response to acid-alkaline are lost.

The Effect of Rapid Thermal Processing on the Electrical Characteristics of Polysilicon Gate Mos Capacitors

1987 ◽  
Vol 92 ◽  
Author(s):  
Susan B. Felch ◽  
David T. Hodul ◽  
Mak Salimian Mak Salimian
Keyword(s):  
Ion Implantation ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Mos Capacitors ◽  
Patterned Wafers ◽  
Annealing Conditions ◽  
Rapid Annealing ◽  
Polysilicon Gate ◽  
Annealing Cycle ◽  
Wet Etch

ABSTRACTRapid thermal processing has previously been observed to affect the dielectric integrity of thin oxides.' In order to study this phenomenon in more detail, we have fabricated a set of wafers with 290 Å thick gate oxide and patterned pads of 2000 Å thick doped polysilicon. Some of the pads were patterned with a wet etch, while others were dry etched in a commercial reactive ion etcher (RIE), which is suspected to be a damaging process. To simulate a self-aligned MOS process, some of the patterned wafers were also ion implanted with 70 keV, 2E15 As+/cm2 . Subsequently, all of the wafers were rapidly annealed in a Varian RTP-800 lamp annealer under a variety of conditions (lO00-1100°C, 10-30 sec), and the breakdown characteristics of the MOS capacitors were measured. A few control samples were annealed in a furnace. It was found that the rapid annealing cycle without ion implantation or dry etching caused no deterioration of the oxide quality. However, rapid annealing after either RIE or implantation does result in oxide breakdowns at lower voltages, with those capacitors having higher perimeter-toarea ratios affected to a greater degree. The effect of capacitor shape and annealing conditions on breakdown statistics and uniformity will be presented and discussed in light of possible ion bombardment damage during RIE and oxide charging during ion implantation. Several mechanisms explaining the breakdown properties will be discussed.

Ultra Thin High Quality Ta2O5 Gate Dielectrics Prepared by In-situ Rapid Thermal Processing

1999 ◽  
Vol 567 ◽  
Author(s):  
H. F. Luan ◽  
S. J. Lee ◽  
C. H. Lee ◽  
A. Y. Mao ◽  
R. Vrtis ◽  
...  
Keyword(s):  
Leakage Current ◽  
Thermal Processing ◽  
Gate Dielectrics ◽  
Rapid Thermal Processing ◽  
Interface Properties ◽  
High Quality

ABSTRACTIn this paper, ultra thin CVD Ta2O5 stacked gate dielectrics (Teq∼14Å-22Å) was fabricated by in-situ RTP processing. The leakage current of Ta2O5 devices is 103× lower leakage current compared to SiO2 of identical thickness for devices with Teq between 18Å-22Å. While Teq<18Å, the leakage current follows same train and J∼10−3A/cm2 for Ta2O5 stacked gate dielectrics with Teq=14Å. Superior interface properties and reliability have been obtained.

Sign in / Sign up

Export Citation Format

Share Document