The Effect of Rapid Thermal Processing on the Electrical Characteristics of Polysilicon Gate Mos Capacitors

1987 ◽  
Vol 92 ◽  
Author(s):  
Susan B. Felch ◽  
David T. Hodul ◽  
Mak Salimian Mak Salimian
Keyword(s):  
Ion Implantation ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Mos Capacitors ◽  
Patterned Wafers ◽  
Annealing Conditions ◽  
Rapid Annealing ◽  
Polysilicon Gate ◽  
Annealing Cycle ◽  
Wet Etch

ABSTRACTRapid thermal processing has previously been observed to affect the dielectric integrity of thin oxides.' In order to study this phenomenon in more detail, we have fabricated a set of wafers with 290 Å thick gate oxide and patterned pads of 2000 Å thick doped polysilicon. Some of the pads were patterned with a wet etch, while others were dry etched in a commercial reactive ion etcher (RIE), which is suspected to be a damaging process. To simulate a self-aligned MOS process, some of the patterned wafers were also ion implanted with 70 keV, 2E15 As+/cm2 . Subsequently, all of the wafers were rapidly annealed in a Varian RTP-800 lamp annealer under a variety of conditions (lO00-1100°C, 10-30 sec), and the breakdown characteristics of the MOS capacitors were measured. A few control samples were annealed in a furnace. It was found that the rapid annealing cycle without ion implantation or dry etching caused no deterioration of the oxide quality. However, rapid annealing after either RIE or implantation does result in oxide breakdowns at lower voltages, with those capacitors having higher perimeter-toarea ratios affected to a greater degree. The effect of capacitor shape and annealing conditions on breakdown statistics and uniformity will be presented and discussed in light of possible ion bombardment damage during RIE and oxide charging during ion implantation. Several mechanisms explaining the breakdown properties will be discussed.

Transient And Spatial Radiative Properties Of Patterned Wafers During Rapid Thermal Processing

1995 ◽  
Vol 387 ◽  
Author(s):  
Peter Y. Wong ◽  
Ioannis N. Miaoulis ◽  
Cynthia G. Madras
Keyword(s):  
Heat Transfer ◽  
Heat Source ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Temporal Variations ◽  
Radiative Properties ◽  
Wafer Surface ◽  
Patterned Wafers ◽  
Thermal Radiative Properties ◽  
Dynamic Variations

AbstractTemperature measurements and processing uniformity continue to be major issues in Rapid Thermal Processing. Spatial and temporal variations in thermal radiative properties of the wafer surface are sources of non-uniformities and dynamic variations. These effects are due to changes in spectral distribution (wafer or heat source), oxidation, epitaxy, silicidation, and other microstructural transformations. Additionally, other variations are induced by the underlying (before processing) and developing (during processing) patterns on the wafer. Numerical simulations of Co silicidation that account for these factors are conducted to determine the radiative properties, heat transfer dynamics, and resultant processing uniformity.

Low-Temperature PECVD Polysilicon Crystallization by Rapid Thermal Processing

1998 ◽  
Vol 508 ◽  
Author(s):  
Mark Stewart ◽  
Howard Hovagimian ◽  
Jecko Arakkal ◽  
Sambit Saha ◽  
Miltiadis K. Hatalis
Keyword(s):  
Thermal Processing ◽  
Solid Phase ◽  
Rapid Thermal Processing ◽  
Statistical Design ◽  
Laser Crystallization ◽  
Polysilicon Film ◽  
Pressure Surface ◽  
Glass Substrates ◽  
Annealing Conditions ◽  
Scan Speed

AbstractThis work investigates the solid phase crystallization of PECVD amorphous silicon films by rapid thermal processing (RTP) as an alternative to laser crystallization. It is shown that PECVD films can be crystallized by RTP at temperatures compatible with glass substrates. A statistical design approach was used to investigate the effect of the various deposition and annealing conditions on the crystallization temperature, material properties and TFT device performance. The investigated variables include deposition temperature, rf power, pressure, surface treatments, dehydrogenation treatment, source gas, dilutant gas, and RTP scan speed. Important deposition and crystallization parameters will be discussed regarding polysilicon film optimization.

Ion Implantation-Induced Defects and the Influence of Titanium Silicidation

1998 ◽  
Vol 510 ◽  
Author(s):  
D.Z. Chi ◽  
S. Ashok ◽  
D. Theodore
Keyword(s):  
Ion Implantation ◽  
Thermal Processing ◽  
Thermal Evolution ◽  
Deep Level ◽  
Rapid Thermal Processing ◽  
Current Voltage ◽  
Transient Spectroscopy ◽  
Thermal Signature ◽  
P Type ◽  
Induced Defects

AbstractThermal evolution of ion implantation-induced defects and the influence of concurrent titanium silicidation in pre-amorphized p-type Si (implanted with 25 KeV, 1016 cm2Si+) under rapid thermal processing (RTP) have been investigated. Presence of implantation-induced electrically active defects has been confirmed by current-voltage (IV) and deep level transient spectroscopy (DLTS) measurements. DLTS characterization results show that the evolution of electrically active defects in the Si implanted samples under RTP depend critically on the RTP temperature: Hole traps HI (0.33 eV) and H4 (0.47 eV) appear after the highest temperature (950 °C) anneal, while a single trap H3 (0.26 eV) shows up at lower anneal temperatures (≤ 900 °C). The thermal signature of H4 defect is very similar to that of the iron interstitial while those of HI and H3 levels appear to originate from some interstitial-related defects, possibly complexes. A most interesting finding is that the above interstitial related defects can be eliminated completely with Ti silicidation, apparently a result of vacancy injection. However the silicidation process itself introduces a new H2 (0.30 eV) level, albeit at much lower concentration. This same H2 level is also seen in unimplanted samples under RTP. The paper will present details of defect evolution under various conditions of RTP for samples with and without the self-implantation and silicidation.

Ge nanocrystals in MOS-memory structures produced by molecular-beam epitaxy and rapid-thermal processing

2004 ◽  
Vol 830 ◽  
Author(s):  
A. Nylandsted Larsen ◽  
A. Kanjilal ◽  
J. Lundsgaard Hansen ◽  
P. Gaiduk ◽  
P. Normand ◽  
...  
Keyword(s):  
Molecular Beam Epitaxy ◽  
Process Parameters ◽  
Gate Voltage ◽  
Thermal Processing ◽  
Molecular Beam ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Mos Capacitors ◽  
Very High ◽  
Ge Nanocrystals

ABSTRACTA method of forming a sheet of Ge nanocrystals in a SiO2 layer based on molecular beam epitaxy (MBE) and rapid thermal processing (RTP) is presented. The method takes advantage of the very high precision by which a very thin Ge layer can be deposited by MBE. With proper choice of process parameters the nanocrystal size can be varied between ∼3 and ∼8 nm and the area-density between ∼1×1011 and ∼1×1012 dots/cm2. The tunneling oxide thickness is determined by the thickness of a thermally grown SiO2 layer, and is typically 4 nm. C-V measurements of MOS capacitors reveal hole and electron injection from the substrate into the nanocrystals. Memory windows of about 0.2 and 0.5 V for gate-voltage sweeps of 3 and 6 V, respectively, are achieved.

The Effect of Multilayer Patterns on Thermal Stress During Rapid Thermal Processing

1996 ◽  
Vol 429 ◽  
Author(s):  
Jeffrey P. Hebbi ◽  
Klavs F. Jensen
Keyword(s):  
Plastic Deformation ◽  
Thermal Stress ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing Parameters ◽  
Radiative Properties ◽  
Stress Fields ◽  
Transport Models ◽  
Patterned Wafers ◽  
Side Illumination

AbstractMultilayer patterns can lead to temperature non-uniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Thermal stress can, in turn, cause problems such as photolithography overlay errors and degraded device performance through plastic deformation. In this work, the temperature and stress fields in patterned wafers are simulated using detailed finite-element based reactor transport models coupled with electromagnetic theory for predicting radiative properties of multilayers. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results are presented for two generic two-dimensional axi-symmetric reactors employing single and double side illumination. The effect of patterns and processing parameters are explored, and strategies for avoiding pattern induced plastic deformation are evaluated.

High Quality Ultra-Thin Tunneling N2O Oxides Fabricated by Rtp

1993 ◽  
Vol 303 ◽  
Author(s):  
G. W. Yoon ◽  
A. B. Joshi ◽  
J. Kim ◽  
D. L. Kwong
Keyword(s):  
Thermal Processing ◽  
Dielectric Breakdown ◽  
Gate Dielectrics ◽  
Rapid Thermal Processing ◽  
Time Dependent ◽  
High Quality ◽  
Mos Capacitors ◽  
Time Dependent Dielectric Breakdown ◽  
Stress Induced Leakage Current ◽  
As Stress

ABSTRACTIn this paper, a detailed reliability investigation is presented for ultra-thin tunneling (∼50 Å) oxides grown in N2O ambient using rapid thermal processing (RTP). These N2Oss-oxides are compared with oxides of identical thickness grown in O2 ambient by RTP. The reliability investigations include time-dependent dielectric breakdown as well as stress-induced leakage current in MOS capacitors with these gate dielectrics. Results show that ultra-thin N2O-oxides show much improved reliability as compared to oxide grown in O2 ambient.

Characterization of Process Uniformity and Control of Titanium Silicide Formed by Rapid Thermal Processing (RTP)

1987 ◽  
Vol 92 ◽  
Author(s):  
David Hodul David Hodul ◽  
Sandeep Mehta Sandeep Mehta
Keyword(s):  
Thermal Processing ◽  
Low Temperatures ◽  
Rapid Thermal Processing ◽  
Titanium Silicide ◽  
Film Properties ◽  
Rapid Annealing ◽  
Oxygen Contamination ◽  
Process Uniformity ◽  
And Control

ABSTRACTSputtered titanium films with thicknesses in the range of 300 to 1200Å were processed in a commercial rapid annealing system to form TiSi2 films. The films were first reacted at low temperatures (500-700°C), etched in ammonia/peroxide solution, and then reacted at 850-900°C to simulate a typical self-alignedsilicide (salicide) process. A method to correctfor dynamic temperature nonuniformities and the resulting etch nonuniformities will be discussed. Sheet resistance maps of the resulting films will be presented. In addition, film properties were measured as a function of annealing ambient in particular, the effects of oxygen contamination were studied.

Characteristics of Arsenic Doped Polycrystalline Silicon-Gate Capacitors After Rapid Thermal Processing

1987 ◽  
Vol 106 ◽  
Author(s):  
R. Angelucci ◽  
C. Y. Wong ◽  
J. Y.-C. Sun ◽  
G. Scilla ◽  
P. A. McFarland ◽  
...  
Keyword(s):  
Work Function ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Polycrystalline Silicon ◽  
Rapid Thermal Processing ◽  
Interface States ◽  
Fixed Charges ◽  
Polysilicon Gate

ABSTRACTThe feasibility and advantages of using rapid thermal annealing to achieve a proper n+ polysilicon work function are demonstrated. Our data shows that RTA can be used to activate arsenic in the polysilicon gate after a regular furnace anneal or to diffuse and activate arsenic without any prior furnace anneal. Interface states and fixed charges due to RTA can be annealed out at 500°C for 30 min in forming gas. New insights into the diffusion, segregation, and activation of As in polysilicon during furnace and/or rapid thermal annealing have been obtained.

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