Impact of Various In Situ Preoxidation Process Perturbations on Gate Oxide Quality

1994 ◽  
Vol 338 ◽  
Author(s):  
P. K. Roy ◽  
M. Weinhoffer ◽  
R. L. Dyas ◽  
S. Meester
Keyword(s):  
Orthogonal Array ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Poor Quality ◽  
Oxidation Temperature ◽  
Designed Experiment

ABSTRACTThis work describes an orthogonal array (OA8) designed experiment involving several insitu process perturbations during oxidation to develop a 90 Å gate oxide for 0.5μm CMOS technology. The biggest impactors were (i) the insitu preoxidation anneal at oxidation temperature, Tox, (ii) 90% N2 dilution of the ambient during ramp-up, and (iii) lowering the Tox to 850°C. Significant improvements in leakage, breakdown, and wear-out characteristics of the oxide are probably due to the reduction of poor quality ramp oxide grown by 90% N2 dilution and improved Si/SiO2 interfacial substructure attained by the insitu preoxidation anneal.

Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Process Architecture ◽  
Process Complexity ◽  
Mos Gate ◽  
Cluster Tool

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

In-Situ Dual Beam (FIBSEM) Techniques for Probe Pad Deposition and Dielectric Integrity Inspection in 0.2 μm Technology DRAM Single Cells

1999 ◽  
Author(s):  
Gunnar Zimmermann ◽  
Richard Chapman
Keyword(s):  
Electron Beam ◽  
Single Cell ◽  
Single Cells ◽  
Ion Beam ◽  
Gate Oxide ◽  
Ion Milling ◽  
Dual Beam ◽  
Sem Imaging ◽  
Innovative Techniques

Abstract Dual beam FIBSEM systems invite the use of innovative techniques to localize IC fails both electrically and physically. For electrical localization, we present a quick and reliable in-situ FIBSEM technique to deposit probe pads with very low parasitic leakage (Ipara < 4E-11A at 3V). The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance. The buried plate (n-Band), p-well, wordline and bitline of a failing and a good 0.2 μm technology DRAM single cell were contacted. Both cells shared the same wordline for direct comparison of cell characteristics. Through this technique we electrically isolated the fail to a single cell by detecting leakage between the polysilicon wordline gate and the cell diffusion. For physical localization, we present a completely in-situ FIBSEM technique that combines ion milling, XeF2 staining and SEM imaging. With this technique, the electrically isolated fail was found to be a hole in the gate oxide at the bad cell.

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Cmos Process ◽  
Oxide Breakdown ◽  
Time Dependent Dielectric Breakdown ◽  
Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Effect of oxidation temperature on physical and electrical properties of ZrO2 thin-film gate oxide on Ge substrate

2017 ◽  
Vol 642 ◽  
pp. 352-358 ◽  
Author(s):  
Zhen Ce Lei ◽  
Kian Heng Goh ◽  
Nor Ishida Zainal Abidin ◽  
Yew Hoong Wong
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Gate Oxide ◽  
Oxidation Temperature ◽  
Zro2 Thin Film

Electron Scattering in Buried InGaAs MOSFET Channel with HfO2 Gate Oxide

2009 ◽  
Vol 1155 ◽  
Author(s):  
Serge Oktyabrsky ◽  
Padmaja Nagaiah ◽  
Vadim Tokranov ◽  
Sergei Koveshnikov ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
High Mobility ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Interface Layer ◽  
Oxide Interface ◽  
Channel Mobility ◽  
Group Iii ◽  
High K ◽  
Electron Transport Properties ◽  
Group Iii V Semiconductor

AbstractGroup III-V semiconductor materials are being studied as potential replacements for conventional CMOS technology due to their better electron transport properties. However, the excess scattering of carriers in MOSFET channel due to high-k gate oxide interface significantly depreciates the benefits of III-V high-mobility channel materials. We present results on Hall electron mobility of buried QW structures influenced by remote scattering due to InGaAs/HfO2 interface. Mobility in In0.77Ga0.23As QWs degraded from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope changed from T-1.2 to almost T+1.0 in 77-300 K range when the barrier thickness is reduced from 50 to 0 nm. This mobility change is attributed to remote Coulomb scattering due to charges and dipoles at semiconductor/oxide interface. Elimination of the InGaAs/HfO2 interface via introduction of SiOx interface layer formed by oxidation of thin a-Si passivation layer was found to improve the channel mobility. The mobility vs. sheet carrier density shows the maximum close to 2×1012 cm-2.

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