Gate-Prior-To-Isolation Cmos-Technology with Through-The-Gate-Implanted Ultra-Thin Gate Oxides

1999 ◽  
Vol 567 ◽  
Author(s):  
Udo Schwalke ◽  
Christian Gruensfelder ◽  
Alexander Gschwandtner ◽  
Gudrun Innertsberger ◽  
Martin Kerber
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Process Architecture ◽  
Process Complexity ◽  
Mos Gate ◽  
Cluster Tool

ABSTRACTWe have realized direct-tunneling gate oxide (1.6nm) NMOS and PMOS transistors by means of through-the-gate-implantation in a comer parasitics-free shallow-trench-isolation CMOS technology. In order to take full advantage of in-situ cluster-tool processing and to preserve initial wafer-surface quality, the essential part of the MOS gate is fabricated prior to device isolation and through-the-gate-implantation is utilized for well- and channel doping. In addition, a fully-reinforced-gate-oxide-perimeter is provided and trench comer parasitics are eliminated by the advanced process architecture EXTIGATE without increasing process complexity.

Impact of Various In Situ Preoxidation Process Perturbations on Gate Oxide Quality

1994 ◽  
Vol 338 ◽  
Author(s):  
P. K. Roy ◽  
M. Weinhoffer ◽  
R. L. Dyas ◽  
S. Meester
Keyword(s):  
Orthogonal Array ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Poor Quality ◽  
Oxidation Temperature ◽  
Designed Experiment

ABSTRACTThis work describes an orthogonal array (OA8) designed experiment involving several insitu process perturbations during oxidation to develop a 90 Å gate oxide for 0.5μm CMOS technology. The biggest impactors were (i) the insitu preoxidation anneal at oxidation temperature, Tox, (ii) 90% N2 dilution of the ambient during ramp-up, and (iii) lowering the Tox to 850°C. Significant improvements in leakage, breakdown, and wear-out characteristics of the oxide are probably due to the reduction of poor quality ramp oxide grown by 90% N2 dilution and improved Si/SiO2 interfacial substructure attained by the insitu preoxidation anneal.

Colloidal Silica based High Selectivity Shallow Trench Isolation (STI) Chemical Mechanical Polishing (CMP) Slurry

2005 ◽  
Vol 867 ◽  
Author(s):  
Kyoung-Ho Bu ◽  
Brij M. Moudgil
Keyword(s):  
Silicon Nitride ◽  
Chemical Mechanical Polishing ◽  
Colloidal Silica ◽  
Sodium Dodecyl ◽  
Mechanical Polishing ◽  
Wafer Surface ◽  
Shallow Trench Isolation ◽  
Pattern Size ◽  
Trench Isolation ◽  
Silica Slurry

AbstractAmong various properties of chemical mechanical polishing (CMP) slurry, selectivity plays a key role in global planarization of high density and small pattern size shallow trench isolation (STI) process. Lack of adequate selectivity can lead to defects such as dishing and erosion. To improve the selectivity of STI CMP process, CMP characteristics of silica and silicon nitride wafer were investigated using colloidal silica slurry as a function of slurry pH. Sodium dodecyl sulfate (SDS), an anionic surfactant, was added to increase the selectivity of the slurry. As a result, selectivity increased from 3 to 25. It was concluded that selective passivation layer formed on silicon nitride wafer surface at acidic slurry pH range was responsible for the observed selectivity increase. Adsorption characteristics of SDS on silica and silicon nitride were measured as a function of slurry pH and concentration of SDS. As indicated by zeta potential behavior under acidic pH conditions, SDS adsorption on silicon nitride was significantly higher han silica due to the electrostatic forces. Significantly higher SDS coating on silicone nitride seems to have resulted in lubrication layer leading to increased polishing selectivity.

Reliability Issues with Mixed-Signal CMOS Technology

1995 ◽  
Vol 391 ◽  
Author(s):  
Rajeeva Lahri ◽  
Hung-Sheng Chen ◽  
Ji Zhao ◽  
Kamesh Gadepally ◽  
C.S. Teng
Keyword(s):  
Analog Circuits ◽  
Analog Circuit ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Low Noise ◽  
Resistance Change ◽  
Mixed Signal ◽  
Device Architecture ◽  
Device Reliability ◽  
Process Architecture

AbstractIn a Mixed-Signal IC, both digital and analog circuits exist on the same chip. Analog circuit blocks require technology attributes like precise device matching, low parametric drifts and low noise. These requirements raise additional reliability issues, over and above the reliability concerns associated with digital circuits. CMOS device reliability for mixed-signal technologies can be enhanced by modifying device architecture and improving gate oxide integrity. Interconnect metallurgy plays an important role in determining electromigration related contact/via resistance change which may impact matching of devices and resistor pairs. Appropriate source/drain engineering, device design and utilizing nitrided gate oxide has been shown to produce extremely stable devices. This article will cover process architecture and material issues related with device stability and interconnect metallurgy issues related with contact/via stability, especially with W-Plugs.

A Highly Reliable 0.18 μm SOI CMOS Technology for 3.3V/1.8V Operation Using Hybrid Trench Isolation and Dual Gate Oxide

2001 ◽  
Author(s):  
S. Maeda ◽  
K. Shiga ◽  
H. Naruoka ◽  
N. Hattori ◽  
T. Iwamatsu ◽  
...  
Keyword(s):  
Gate Oxide ◽  
Cmos Technology ◽  
Trench Isolation ◽  
Dual Gate ◽  
Soi Cmos
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