A 3-D Integration Strategy in VLSI

ABSTRACTNearly two decades of work in fabricating active devices in small grain LPCVD polysilicon by various workers has shown that the material is generally suitable for junction diodes and MOSFETs [1–10]. Recently, there has been a considerable activity in the domain of beam recrystallization of polysilicon. One of the goals of this effort is 3-D integration for VLSI. These recrystallization techniques require several years of industrywide effort before they become acceptable tools in IC manufacturing. However, there exists a great demand today, especially in large memories, for an SOI MOSFET that can be integrated in existing bulk silicon based technologies.Fortunately, acceptable MOSFETs can be manufactured in small grain poly-silicon without resorting to beam recrystallization [11–13]. One consistent problem with small grain polysilicon MOSFETs has been a high threshold voltage, which makes these devices unacceptable for standard IC applications that require 5V operation. It has been shown that this characteristic can be remedied by proper device design [11–13]. In particular, thin gate insulator, accumulation mode behaviour, and some form of grain boundary passivation, used alone or in a combination, are effective means of reducing threshold voltage.The other problem of the polysilicon devices has been high leakage current. This is a result of defects in polysilicon. It has been shown that grain boundary hydrogenation drastically reduces the leakage current by passivating these defects [11–13]. As a result, it is possible to manufacture MOSFETs, in small grain LPCVD polysilicon, with on to off current ratio of seven orders of magnitude.With improved device design, it has been possible to build short channel p-channel and n-channel MOSFETs with arbitrary threshold voltage and leakage current of the order of 1 pA/μm channel width. The channel mobility is about 10 cm2/V sec. The on to off current ratio is about seven orders of magnitude. Despite the low mobility, these devices are useful for a variety of high density memory applications.Since no nonstandard materials, tools and processes are required in the fabrication of these devices, manufacturable 3-D integration processes are presently possible with such devices. Besides permitting useful products today, this strategy allows construction of a design and manu-facturing infrastructure that will facilitate infusion of future 3-D concepts in bulk silicon technologies.We have used p-channel devices built in small grain LPCVD polysilicon to develop a 2 μm stacked CMOS process. We have fabricated 64K static RAMs with this process. The cell size is 307 sq.μm and chip size is 55000 sq. mils. The access time is 120 ns. This provides a demonstration of our strategy.