On the compact modelling of Si nanowire and Si nanosheet MOSFETs

In this paper, 3D TCAD simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in Nanowire and Nanosheet structures, are practically same. This characteristic makes possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend the application of the Symmetric Doped Double-Gate Model (SDDGM) model to Nanowires and Nanosheets MOSFETs, with no need to include new parameters. The Model SDDGM is validated for this application using several measured and simulated structures of Nanowires and Nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SmartSPICE circuit simulator.

Effect of metal heat guide structure on the performance of planar Si thermoelectric generator embedded in SiO2 inter-layer dielectric

Heat guide (HG) is a layer providing a heat flux to a desired part in micro thermoelectric generator (µ-TEG). In this work, we experimentally investigated the impact of the HG structure on the thermoelectric voltage of a cavity-free planer-type Si-nanowire (Si-NW) µ-TEG, which is embedded in SiO2 acting as an inter-layer dielectric (ILD). Although the heat flows also through the ILD, a sub-µm-thick HG is able to selectively guide the heat flux to hot side terminal of the µ-TEG, and the µ-TEG performance is improved by increasing the thickness of the HG.

Versatilely tuned vertical silicon nanowire arrays by cryogenic reactive ion etching as a lithium-ion battery anode

Production of high-aspect-ratio silicon (Si) nanowire-based anode for lithium ion batteries is challenging particularly in terms of controlling wire property and geometry to improve the battery performance. This report demonstrates tunable optimization of inductively coupled plasma reactive ion etching (ICP-RIE) at cryogenic temperature to fabricate vertically-aligned silicon nanowire array anodes with high verticality, controllable morphology, and good homogeneity. Three different materials [i.e., photoresist, chromium (Cr), and silicon dioxide (SiO2)] were employed as masks during the subsequent photolithography and cryogenic ICP-RIE processes to investigate their effects on the resulting nanowire structures. Silicon nanowire arrays with a high aspect ratio of up to 22 can be achieved by tuning several etching parameters [i.e., temperature, oxygen/sulfur hexafluoride (O2/SF6) gas mixture ratio, chamber pressure, plasma density, and ion energy]. Higher compressive stress was revealed for longer Si wires by means of Raman spectroscopy. Moreover, an anisotropy of lattice stress was found at the top and sidewall of Si nanowire, indicating compressive and tensile stresses, respectively. From electrochemical characterization, half-cell battery integrating ICP-RIE-based silicon nanowire anode exhibits a capacity of 0.25 mAh cm−2 with 16.67% capacity fading until 20 cycles, which has to be improved for application in future energy storage devices.