Roughness of TFT Gate Metallization and its Impact on Leakage, Threshold Voltage Shift and Mobility

2000 ◽  
Vol 609 ◽  
Author(s):  
A. Nathan ◽  
B. Park ◽  
A. Sazonov ◽  
R.V.R. Murthy
Keyword(s):  
Surface Roughness ◽  
Leakage Current ◽  
Threshold Voltage ◽  
High Surface ◽  
Gate Insulator ◽  
Large Shift ◽  
Cross Sectional ◽  
Threshold Voltage Shift ◽  
Small Shift ◽  
Low Leakage

ABSTRACTA comparison of the performance of aluminium (Al)-gated thin film transistors (TFTs) is presented in which we varied its sputter deposition conditions, such as deposition temperature, process pressure, and power. Gate films deposited at 30°C/5mTorr/300W yield TFT characteristics with low leakage current (~ 10 fA at low VDS), an ON/OFF ratio better than 108, and a mobility of 1.1 cm2/Vs. In contrast, films deposited at 150°C/10mTorr/400W, yield a significant degradation in leakage current (~ 1 pA) and mobility (0.77 cm2/Vs). The degradation stems from the high surface roughness of the a-SiNx:H gate insulator, and hence the TFT channel, caused by hillock formation on the Al gate. In addition, the high roughness leads to a correspondingly large shift in threshold voltage. After one-hour bias stress of +25 V applied to the gate, the shift in threshold voltage is ΔVT ~ 5 V, as compared to the small shift of ΔVT ~ 2.3 V associated with the smoother gate. Also included in our comparison is a TFT whose Al gate is now capped with 20 nm of molybdenum (Mo) to minimize propagation of the gate surface roughness to the active channel. Its cross sectional topography shows the interface smoothness to be as good or better, to yield improved leakage and stability characteristics.

COMPARATIVE INSTABILITIES ANALYSIS FOR a-Si:H BODY-TIED TFT (BT-TFT) AND FLOATING BODY TFT (FB-TFT) UNDER BIAS TEMPERATURE STRESSING (BTS)

2008 ◽  
Vol 22 (05) ◽  
pp. 337-341
Author(s):  
YONG K. LEE ◽  
SUNG-HOON CHOA
Keyword(s):  
Silicon Nitride ◽  
Threshold Voltage ◽  
Gate Insulator ◽  
Floating Body ◽  
Negative Bias ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Stress ◽  
Hole Trapping

The a- Si:H thin film transistors TFT with silicon nitride as a gate insulator have been stressed with negative and positive bias to realize the instability mechanisms. With proposed BT-TFT and FB-TFT devices, it is found that the threshold voltages of both BT-TFT and BT-TFT devices are positively shifted under positive bias stress and then negatively shifted for negative bias stress. The positive threshold voltage shift is due to the electron trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The negative threshold voltage shift is mainly due to hole trapping and/or electron de-trapping in the silicon nitride or at the a- Si:H /silicon nitride interface. The positive or negative threshold voltage shift keeps increasing with increasing positive or negative gate bias for both BT-TFT and FB-TFT devices. However, as far as the threshold voltage shift slope is concerned, under positive bias stress, both BT-TFT and FB-TFT devices are similar to each other. On the other hand, under negative bias stress, BT-TFT shift amount is much less than one for the FB-TFT device.

Investigation on the Electrical Stability of 5,11-Bis(triethylsilylethynyl)anthradithiophene Thin-Film Transistors

2021 ◽  
Vol 21 (3) ◽  
pp. 1754-1760
Author(s):  
Joel Ndikumana ◽  
Jyothi Chintalapalli ◽  
Jin-Hyuk Kwon ◽  
Jin-Hyuk Bae ◽  
Jaehoon Park
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Ambient Air ◽  
Gate Insulator ◽  
Hydroxyl Groups ◽  
Electrical Stability ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Domain Boundaries

We investigate the effects of environmental conditions on the electrical stability of spin-coated 5,11-bis(triethylsilylethynyl)anthradithiophene (TES-ADT) thin-film transistors (TFTs) in which crosslinked poly(4-vinylphenol-co-methyl methacrylate) (PVP-co-PMMA) was utilized as a gate insulator layer. Atomic force microscopy observations show molecular terraces with domain boundaries in the spin-coated TEST-ADT semiconductor film. The TFT performance was observed to be superior in the ambient air condition. Under negative gate-bias stress, the TES-ADT TFTs showed a positive threshold voltage shift in ambient air and a negative threshold voltage shift under vacuum. These results are explained through a chemical reaction between water molecules in air and unsubstituted hydroxyl groups in the cross-linked PVP-co-PMMA as well as a charge-trapping phenomenon at the domain boundaries in the spin-coated TES-ADT semiconductor.

Performance of ZnO TFTs with AlN as Insulator

2007 ◽  
Vol 1035 ◽  
Author(s):  
Maria Merlyne De Souza ◽  
Richard B Cross ◽  
Suhas Jejurikar ◽  
K P Adhi
Keyword(s):  
Surface Roughness ◽  
Threshold Voltage ◽  
Rf Sputtering ◽  
Interface States ◽  
Aluminium Nitride ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Positive Threshold ◽  
The Stability

AbstractThe performance of ZnO TFTs fabricated via RF sputtering, with Aluminium Nitride (AlN) as the underlying insulator are reported. The surface roughness of ZnO with AlN is lower than that with SiN by at least 5 times, and that with SiO2 by 30 times. The resulting mobility for the three insulators AlN, SiN, SiO2 using identical process is found to be 3, 0.2-0.7 and 0.1-0.25 cm2/Vs respectively. There does not appear to be any corresponding improvement in the stability of the AlN devices. The devices demonstrate significant positive threshold voltage shift with positive gate bias and negative threshold voltage shift with negative gate bias. The underlying cause is surmised to be ultra-fast interface states in combination with bulk traps in the ZnO.

scholarly journals Remarkable Stability Improvement of ZnO TFT with Al2O3 Gate Insulator by Yttrium Passivation with Spray Pyrolysis

Nanomaterials ◽  
2020 ◽  
Vol 10 (5) ◽  
pp. 976 ◽  
Author(s):  
Jewel Kumer Saha ◽  
Ravindra Naik Bukke ◽  
Narendra Naik Mude ◽  
Jin Jang
Keyword(s):  
Spray Pyrolysis ◽  
Threshold Voltage ◽  
Moisture Absorption ◽  
Thin Film Transistor ◽  
Gate Insulator ◽  
Zno Films ◽  
Threshold Voltage Shift ◽  
Bias Temperature Stress ◽  
The Stability ◽  
The Impact

We report the impact of yttrium oxide (YOx) passivation on the zinc oxide (ZnO) thin film transistor (TFT) based on Al2O3 gate insulator (GI). The YOx and ZnO films are both deposited by spray pyrolysis at 400 and 350 °C, respectively. The YOx passivated ZnO TFT exhibits high device performance of field effect mobility (μFE) of 35.36 cm2/Vs, threshold voltage (VTH) of 0.49 V and subthreshold swing (SS) of 128.4 mV/dec. The ZnO TFT also exhibits excellent device stabilities, such as negligible threshold voltage shift (∆VTH) of 0.15 V under positive bias temperature stress and zero hysteresis voltage (VH) of ~0 V. YOx protects the channel layer from moisture absorption. On the other hand, the unpassivated ZnO TFT with Al2O3 GI showed inferior bias stability with a high SS when compared to the passivated one. It is found by XPS that Y diffuses into the GI interface, which can reduce the interfacial defects and eliminate the hysteresis of the transfer curve. The improvement of the stability is mainly due to the diffusion of Y into ZnO as well as the ZnO/Al2O3 interface.

NiO Development on FeCrAl Substrate for Catalytic Converter Using Ultrasonic and Nickel Electroplating Methods

2010 ◽  
Vol 129-131 ◽  
pp. 1262-1266 ◽  
Author(s):  
Darwin Sebayang ◽  
Putrasari Yanuandri ◽  
Sulaiman B. Hasan ◽  
Pudji Untoro
Keyword(s):  
Surface Roughness ◽  
Surface Area ◽  
Catalytic Converter ◽  
Ultrasonic Method ◽  
High Surface ◽  
High Surface Area ◽  
Irregular Surface ◽  
Cross Sectional ◽  
Nickel Electroplating ◽  
Area Development

The irregular surface roughness morphology due to ultrasonic method was used approach for increasing the high surface area of substrate and catalyst. The purpose of this paper is to show the ultrasonic and nickel electroplating methods for NiO automotive catalyst development on FeCrAl substrate. The process began with pretreatment of FeCrAl using SiC and/or Al2O3 solution agitating by ultrasonic and followed with nickel electroplating. The oxidation test was conducted for developing the NiO. The physical morphology structure of the presence NiO on the FeCrAl substrate was analyzed using scanning electron microscope (SEM) in combination with energy dispersive X-ray spectroscopy (EDS). The cross sectional observation show the NiO catalyst completely existed on the FeCrAl. The ultrasonic method increases the irregular surface roughness morphology on FeCrAl substrate that influenced the homogeneous and stability of nickel electroplating and NiO surface area development.

scholarly journals A New 8T SRAM Circuit with Low Leakage and High Data Stability Idle Mode at 70nm Technology

2017 ◽  
Vol 10 (1) ◽  
pp. 86-93 ◽  
Author(s):  
P Raikwal ◽  
V Neema ◽  
A Verma
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
High Threshold ◽  
Idle Mode ◽  
High Data ◽  
Low Leakage ◽  
Noise Margin ◽  
Threshold Voltages ◽  
Sram Cell ◽  
Low Threshold

Memory has been facing several problems in which the leakage current is the most severe. Many techniques have been proposed to withstand leakage control such as power gating and ground gating. In this paper a new 8T SRAM cell, which adopts a single bit line scheme has been proposed to limit the leakage current as well as to gain high hold static noise margin. The proposed cell with low threshold voltage, high threshold voltage and dual threshold voltage are used to effectively reduce leakage current, and delay. Additionally, the comparison has been performed between conventional 6T SRAM cell and the new 8T SRAM cell. The proposed circuit consumes 671.22 pA leakage current during idle state of the circuit which is very less as compare to conventional 6T SRAM cell with sleep and hold transistors and with different β ratio. The proposed new 8T SRAM cell shows highest noise immunity 0.329mv during hold state. Furthermore, the proposed new 8T SRAM circuit represents minimum read and write access delays 114.13ps and 38.56ps respectively as compare to conventional 6T SRAM cell with different threshold voltages and β ratio.

scholarly journals 3D Numerical Simulation of a Z Gate Layout MOSFET for Radiation Tolerance

Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 659 ◽  
Author(s):  
Ying Wang ◽  
Chan Shan ◽  
Wei Piao ◽  
Xing-ji Li ◽  
Jian-qun Yang ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Computer Aided Design ◽  
Oxide Semiconductor ◽  
Radiation Tolerance ◽  
Threshold Voltage Shift ◽  
Radiation Hardened ◽  
Small Footprint ◽  
Aided Design ◽  
First Time

In this paper, for the first time, an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) layout with a Z gate and an improved total ionizing dose (TID) tolerance is proposed. The novel layout can be radiation-hardened with a fixed charge density at the shallow trench isolation (STI) of 3.5 × 1012 cm−2. Moreover, it has the advantages of a small footprint, no limitation in W/L design, and a small gate capacitance compared with the enclosed gate layout. Beside the Z gate layout, a non-radiation-hardened single gate layout and a radiation-hardened enclosed gate layout are simulated using the Sentaurus 3D technology computer-aided design (TCAD) software. First, the transfer characteristics curves (Id-Vg) curves of the three layouts are compared to verify the radiation tolerance characteristic of the Z gate layout; then, the threshold voltage and the leakage current of the three layouts are extracted to compare their TID responses. Lastly, the threshold voltage shift and the leakage current increment at different radiation doses for the three layouts are presented and analyzed.

Fabrication of 0.1 µm channel diamond Metal-Insulator-Semiconductor Field-Effect Transistor

2001 ◽  
Vol 680 ◽  
Author(s):  
Hitoshi Umezawa ◽  
Yoshikazu Ohba ◽  
Hiroaki Ishizaka ◽  
Takuya Arima ◽  
Hirotada Taniuchi ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Gate Insulator ◽  
Short Channel ◽  
Threshold Voltage Shift ◽  
Metal Insulator ◽  
Metal Insulator Semiconductor ◽  
Voltage Shift ◽  
Effect Transistor

ABSTRACTAnalysis of diamond short channel effect is carried out for the first time. 70 nm channel diamond metal-insulator semiconductor field-effect transistor is realized by utilizing new FET fabrication process on the hydrogen-terminated surface conductive layer. This FET is the shortest gate length in diamond FETs. FETs with thick gate insulator of 35 nm show significant threshold voltage shift and degradation of subthreshold slope S by the gate refining. This phenomenon occurs due to the penetration of drain field into channel. However, the degradation of subthreshold performance and threshold voltage shift are hardly observed in 0.17 µm FET with thin gate insulator 15 nm in thickness.

Low leakage current—stacked MgO∕Bi1.5Zn1.0Nb1.5O7 gate insulator— for low voltage ZnO thin film transistors

2006 ◽  
Vol 89 (20) ◽  
pp. 202908 ◽  
Author(s):  
Mi-Hwa Lim ◽  
KyongTae Kang ◽  
Ho-Gi Kim ◽  
Il-Doo Kim ◽  
YongWoo Choi ◽  
...  
Keyword(s):  
Thin Film ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Low Voltage ◽  
Gate Insulator ◽  
Zno Thin Film ◽  
Low Leakage ◽  
Low Leakage Current
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