AlGaN/GaN MIS-HEMTs with a p-GaN Cap Layer

MRS Advances ◽  
2017 ◽  
Vol 3 (3) ◽  
pp. 143-146
Author(s):  
Che-Ching Hsu ◽  
Pei-Chien Shen ◽  
Yi-Nan Zhong ◽  
Yue-Ming Hsin
Keyword(s):  
Leakage Current ◽  
Breakdown Voltage ◽  
Drain Current ◽  
Gate Insulator ◽  
Current Ratio ◽  
Dc Characteristics ◽  
Cap Layer

ABSTRACTIn this study, AlGaN/GaN MIS-HEMTs with a p-GaN cap layer and ALD deposited Al2O3 gate insulator were fabricated. Devices with two different thicknesses of p-GaN cap layers were investigated and compared. AlGaN/GaN MIS-HEMT with an 8-nm p-GaN cap showed a better DC characteristics than device with a 5-nm p-GaN cap. The drain current of 662.9 mA/mm, a high on/off current ratio of 2.67×109 and a breakdown voltage of 672 V were measured in device with an 8-nm p-GaN cap. In addition, lateral leakage current was investigated by using adjacent MIS gate structures with a separation of 3 μm to investigate the leakage current.

The Effect of Channel Recess and Passivation on 4H-SiC MESFETs

2002 ◽  
Vol 742 ◽  
Author(s):  
Ho-Young Cha ◽  
Christopher I. Thomas ◽  
Goutam Koley ◽  
Lester F. Eastman ◽  
Michael G. Spencer
Keyword(s):  
Breakdown Voltage ◽  
Drain Current ◽  
Surface Effects ◽  
Gate Length ◽  
Small Signal ◽  
Saturation Current ◽  
Power Performance ◽  
Dc Characteristics ◽  
Signal Characteristics ◽  
Lower Saturation

ABSTRACTChannel-recessed 4H-SiC MESFETs were fabricated and demonstrated excellent small signal characteristics. A saturated current of 250 − 270 mA/mm at Vgs = 0 V and a maximum transconductance of 40 − 45 mS/mm were measured for channel-recessed devices with a gate length of 0.45 m. The three-terminal breakdown voltages (Vds) range from 120 V to 150 V. The Ft and Fmax of the 2 × 200 m devices were measured to be 14.5 GHz and 40 GHz, respectively. The channel recess technique results in a lower saturation current but higher breakdown voltage which makes it possible for the devices to operate at high voltages. Si3N4 passivation suppresses the instability in DC characteristics and improves CW power performance by reducing the surface effects. Less dispersion in the drain current during a power sweep was observed after passivation.

Off-state drain current and breakdown voltage of AlGaN/GaN MIS-HEMT with multilayered gate insulator

2007 ◽  
Vol 4 (7) ◽  
pp. 2682-2685 ◽  
Author(s):  
S. Yagi ◽  
M. Shimizu ◽  
M. Inada ◽  
H. Okumura ◽  
H. Ohashi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Drain Current ◽  
Gate Insulator

The Effect of Ohmic Contact Location on the Buffer Leakage Current of AlGaN/GaN Heterostructure

2008 ◽  
Vol 600-603 ◽  
pp. 1337-1340
Author(s):  
Young Hwan Choi ◽  
Ji Yong Lim ◽  
Kyu Heon Cho ◽  
In Hwan Ji ◽  
Min Koo Han
Keyword(s):  
Buffer Layer ◽  
Leakage Current ◽  
Ohmic Contact ◽  
Lateral Diffusion ◽  
Drain Current ◽  
Gan Hemt ◽  
Cap Layer ◽  
Type C ◽  
Gan Heterostructure ◽  
Gan Buffer Layer

The effect of ohmic contact location on the buffer leakage current of AlGaN/GaN heterostructure was investigated and the AlGaN/GaN HEMT employing the proposed ohmic contact pattern was fabricated. We have fabricated 3 different types of ohmic patterns; type A - both contacts are on the etched GaN buffer layer, type B - one is on the etched GaN buffer layer and the other is on the unetched GaN cap layer and type C - both contacts are on the unetched GaN cap layer. Our experimental results showed that the ohmic contact on GaN buffer increased the buffer leakage current due to the lateral diffusion of ohmic metals. The proposed AlGaN/GaN HEMT successfully decreased the leakage current and did not affect the forward drain current and the transconductance.

Characteristics of all-OMCVD Grown GaAs MESFETS on Si Substrates

1988 ◽  
Vol 126 ◽  
Author(s):  
Jhang Woo Lee ◽  
R. M. McCullough ◽  
R. H. Morrison
Keyword(s):  
Leakage Current ◽  
Breakdown Voltage ◽  
Buffer Layers ◽  
Low Background ◽  
Si Substrates ◽  
Turn On ◽  
Gaas Mesfet ◽  
Dc Characteristics ◽  
Key Factor ◽  
Background Doping

ABSTRACTWe present DC characteristics of all-OMCVD grown GaAs MESFET structures on Si substrates with unintentionally doped GaAs or AlGaAs buffer layers. MESFETs fabricated in two and three inch GaAs on Si wafers pinch off well and exhibit reasonably high transconductances up to 110 mS/mm for 1 μm gate devices. The reverse Schottky breakdown voltage of the MESFET gate is as high as 15 V and the forward turn on voltage is ∼0.65 V. The ohmic isolation is comparable to the typical homoepitaxial layer with a leakage current of 100 nA at a 1 V bias. The low background doping levels of unintentionally doped GaAs buffer layers is the key factor for this successful MESFET operation.

Characteristics of All-Omcvd Grown GaAs Mesfets on Si Substrates

1988 ◽  
Vol 116 ◽  
Author(s):  
Jhang Woo Lee ◽  
R. E. McCullough ◽  
R. H. Morrison
Keyword(s):  
Leakage Current ◽  
Breakdown Voltage ◽  
Buffer Layers ◽  
Low Background ◽  
Si Substrates ◽  
Turn On ◽  
Gaas Mesfet ◽  
Dc Characteristics ◽  
Key Factor ◽  
Background Doping

AbstractWe present DC characteristics of all-OMCVD grown GaAs MESFET structures on Si substrates with unintentionally doped GaAs or AlGaAs buffer layers. MESFETs fabricated in two and three inch GaAs on Si wafers pinch off well and exhibit reasonably high transconductances up to 110 mS/mm for 1 µm gate devices. The reverse Schottky breakdown voltage of the MESFET gate is as high as 15 V and the forward turn on voltage is ~0.65 V. The ohmic isolation is comparable to the typical homoepitaxial layer with a leakage current of 100 nA at a I V bias. The low background doping levels of unintentionally doped GaAs buffer layers is the key factor for this successful MESFET operation.

Fabrication of IGZO and In2O3-channel Ferroelectric-gate Thin Film Transistors

2010 ◽  
Vol 1250 ◽  
Author(s):  
tomohiro Oiwa ◽  
Eisuke Tokumitsu
Keyword(s):  
Field Effect ◽  
Charge Injection ◽  
Drain Current ◽  
Gate Insulator ◽  
Field Effect Mobility ◽  
Current Ratio ◽  
Injection Type ◽  
Subthreshold Voltage ◽  
A Charge ◽  
Voltage Swing

AbstractWe have fabricated and characterized ferroelectric-gate TFTs using In-Ga-Zn-O (IGZO) or In2O3 as a channel material. The ferroelectric gate insulator used in this work is (Bi,La)4Ti3O12 (BLT). We observed normal n-channel transistor operation for both IGZO and In2O3-channel TFTs. However, a charge injection type hysteresis was observed for IGZO channel TFTs in drain current – gate voltage (ID-VG) characteristics. Post fabrication anneal at 300oC reduced the charge-injection-tyoe hystereesis and the subthreshold swing was also improved from 0.27 to 0.19 V/decade. On the other hand, when the In2O3 was used as a channel, hysteresis due to the ferroelectric gate insulator was clearly observed in ID-VG characteristics. A memory window of 2V, a subthreshold voltage swing of 0.35V/decade, a field-effect mobility of 1.6 cm2/Vs, and a on/off drain current ratio of more than 10^6 were obtained.

A 3-D Integration Strategy in VLSI

1984 ◽  
Vol 33 ◽  
Author(s):  
Satwinder D. S. Malhi
Keyword(s):  
Grain Boundary ◽  
Leakage Current ◽  
Threshold Voltage ◽  
Gate Insulator ◽  
Access Time ◽  
Cmos Process ◽  
Device Design ◽  
Bulk Silicon ◽  
Short Channel ◽  
Current Ratio

ABSTRACTNearly two decades of work in fabricating active devices in small grain LPCVD polysilicon by various workers has shown that the material is generally suitable for junction diodes and MOSFETs [1–10]. Recently, there has been a considerable activity in the domain of beam recrystallization of polysilicon. One of the goals of this effort is 3-D integration for VLSI. These recrystallization techniques require several years of industrywide effort before they become acceptable tools in IC manufacturing. However, there exists a great demand today, especially in large memories, for an SOI MOSFET that can be integrated in existing bulk silicon based technologies.Fortunately, acceptable MOSFETs can be manufactured in small grain poly-silicon without resorting to beam recrystallization [11–13]. One consistent problem with small grain polysilicon MOSFETs has been a high threshold voltage, which makes these devices unacceptable for standard IC applications that require 5V operation. It has been shown that this characteristic can be remedied by proper device design [11–13]. In particular, thin gate insulator, accumulation mode behaviour, and some form of grain boundary passivation, used alone or in a combination, are effective means of reducing threshold voltage.The other problem of the polysilicon devices has been high leakage current. This is a result of defects in polysilicon. It has been shown that grain boundary hydrogenation drastically reduces the leakage current by passivating these defects [11–13]. As a result, it is possible to manufacture MOSFETs, in small grain LPCVD polysilicon, with on to off current ratio of seven orders of magnitude.With improved device design, it has been possible to build short channel p-channel and n-channel MOSFETs with arbitrary threshold voltage and leakage current of the order of 1 pA/μm channel width. The channel mobility is about 10 cm2/V sec. The on to off current ratio is about seven orders of magnitude. Despite the low mobility, these devices are useful for a variety of high density memory applications.Since no nonstandard materials, tools and processes are required in the fabrication of these devices, manufacturable 3-D integration processes are presently possible with such devices. Besides permitting useful products today, this strategy allows construction of a design and manu-facturing infrastructure that will facilitate infusion of future 3-D concepts in bulk silicon technologies.We have used p-channel devices built in small grain LPCVD polysilicon to develop a 2 μm stacked CMOS process. We have fabricated 64K static RAMs with this process. The cell size is 307 sq.μm and chip size is 55000 sq. mils. The access time is 120 ns. This provides a demonstration of our strategy.

Application of GaAs-AlGaAs Superlattice Structure for Fabricating High Breakdown Voltage Power MISFET

1989 ◽  
Vol 160 ◽  
Author(s):  
W.C. Liu ◽  
W.S. Lour ◽  
R.L. Wang ◽  
C.Y. Sun ◽  
W.C. Hsu
Keyword(s):  
Buffer Layer ◽  
Breakdown Voltage ◽  
Deep Level ◽  
Drain Current ◽  
Low Noise ◽  
Gate Insulator ◽  
Superlattice Structure ◽  
Active Channel ◽  
Buffer Structure ◽  
Impurities And Defects

AbstractA new power MISFET with undoped GaAs-Al0.3Ga0.7As superlattice gate “insulator” and buffer structure has been fabricated successfully. The superlattice gate “insulator” exhibits a much higher gate breakdown voltage( >35V) with very low prebreakdown leakage current and a lower gate capacitance (C ). Due to the existence of gate “insulator”, a higher carrier concentration can be employed in the active channel which improves the output drain current capability and transconductance. If the gate length is reduced to 1 um, a higher transconductance up to 330 mS/mm can be expected.The insertion of superlattice buffer structure, between active channel and buffer layer offers an excellent carrier confinement barrier and gives an interface degraded region smaller than 40A. In addition, the superlattice buffer structure can getter greatly deep level impurities and defects from substrate or buffer layer. In summary, the proposed MISFET structure is suitable for high power, high frequency and low noise applications.

Suppression of Hole Current in Graphene Transistors with N-Type Doped SiC Source/Drain Regions

2012 ◽  
Vol 717-720 ◽  
pp. 679-682 ◽  
Author(s):  
Yuichi Nagahisa ◽  
Eisuke Tokumitsu
Keyword(s):  
Graphene Layer ◽  
Doping Concentration ◽  
Drain Current ◽  
The Other ◽  
Gate Insulator ◽  
High Temperature Annealing ◽  
Current Ratio ◽  
Ambipolar Behavior ◽  
Heavily Doped ◽  
Hole Current

To achieve graphene channel transistors which have high on/off drain current ratio and unipolar behavior of drain current – gate voltage (ID-VG) characteristics, we fabricated and characterized the top gated graphene channel transistors with n-type doped SiC source/drain regions. Graphene layer was formed on SiC by high temperature annealing in vacuum, and Al2O3 was used as a gate insulator. For the graphene channel transistor with heavily doped n-SiC source/drain regions (doping concentration ND=4.5x1019cm-3) and a 4~6ML graphene channel, ambipolar behavior was observed. On the other hand, when ND was reduced to 4.5x1018cm-3 and a thin graphene layer was used, the suppression of hole current in ID-VG curve was observed.

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