Instability in a-Si:H Thin-Film Transistor: A New Method to Discriminate Between Charge Injection and Defect Creation

1992 ◽  
Vol 258 ◽  
Author(s):  
P. Foglietti ◽  
G. Fortunato ◽  
L. Mariucci ◽  
V. Parisi
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Close Correlation ◽  
Gate Insulator ◽  
Flat Band ◽  
Flat Band Voltage ◽  
Instability Mechanism ◽  
Insulator Interface ◽  
Different Temperatures

ABSTRACTIn the present work, in order to discriminate the main source of instability in a-Si:H TFTs, the determination of both threshold voltage and flat-band voltage has been performed after bias-stressing the devices with different gate voltages and at different temperatures. Flat-band voltage was determined by the space-charge photomodulation technique. From the close correlation observed between the two quantities, we conclude that the predominant instability mechanism is represented by change in the gate insulator charge at and near the semiconductor/insulator interface.

Electrical Characteristics of Ni-CNT-SiO2-SiC Structured 4H-SiC MIS Capacitors

2015 ◽  
Vol 15 (10) ◽  
pp. 7542-7545
Author(s):  
Taeseop Lee ◽  
Min-Seok Kang ◽  
Tae-Jun Ha ◽  
Sang-Mo Koo
Keyword(s):  
Gate Insulator ◽  
Flat Band ◽  
Electrical Characteristics ◽  
Flat Band Voltage ◽  
Voltage Shift ◽  
Insulator Interface ◽  
Current Densities ◽  
Mis Capacitors

In this study, the electrical characteristics of Ni-CNT-SiO2-SiC structured 4H-SiC MIS capacitors were investigated. The effect of CNTs in the gate/insulator interface have been characterized by C–V measurement at 300 to 500K and J–V have also been measured. The experimental flat-band voltage tends to change with or without CNTs. Current densities of both devices are observed a negligible difference up to 3 V. It has been found that adding CNTs and/or change of temperature can help to control the positive and/or negative flat-band voltage shift.

Determination of the Defect Redistribution and Charge Injection Contributions to the a-Si:H Thin-Film Transistor Instability

1994 ◽  
Vol 336 ◽  
Author(s):  
R. Carluccio ◽  
A. Pecora ◽  
D. Massimiani ◽  
G. Fortunato
Keyword(s):  
Thin Film ◽  
Silicon Dioxide ◽  
Field Effect ◽  
Thin Film Transistor ◽  
High Stress ◽  
Charge Injection ◽  
Gate Insulator ◽  
Parasitic Resistance ◽  
Moderate Stress

ABSTRACTThe effects of bias-stressing n- and p-channel thin-film transistors, employing thermal silicon dioxide as gate insulator, have been analysed by using different techniques, including field-effect, space-charge photomodulation and photo-induced discharge. Photo-induced discharge experiments have pointed out as parasitic resistance effects can be present in p-channel devices. In order to reduce this problem, thin active layer p-channel devices have been fabricated and, combining these results to those relative to the n-channel transistors, we deduced a predominance of charge injection at low and moderate stress-biases while at high-stress biases modifications in the density of states take place.

Determination of intrinsic mobility of a bilayer oxide thin-film transistor by pulsedI–Vmethod

2017 ◽  
Vol 28 (17) ◽  
pp. 175201 ◽  
Author(s):  
Hyunsuk Woo ◽  
Taeho Kim ◽  
Jihyun Hur ◽  
Sanghun Jeon
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Oxide Thin Film

scholarly journals Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

2019 ◽  
Vol 35 (2) ◽  
Author(s):  
Bui Nguyen Quoc Trinh
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Gate Insulator ◽  
Current Ratio ◽  
Memory State ◽  
Small Loss ◽  
Memory Circuit ◽  
Novel Concept ◽  
Data Reading

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi3.25La0.75Ti3O12 and PbZr0.52TiO0.48O3 (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle. Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

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