Process Uniformity and Electrical Characteristics of Thin Gate Dielectrics Grown by Ramped-Temperature Transient Rapid Thermal Oxidation of Silicon

1989 ◽  
Vol 146 ◽  
Author(s):  
Mehrdad M. Moslehit ◽  
Ahmad Kermani
Keyword(s):  
Thermal Oxidation ◽  
Gate Dielectrics ◽  
Electrical Characteristics ◽  
Thermal Cycles ◽  
Gate Oxides ◽  
Rapid Thermal Oxidation ◽  
Mos Devices ◽  
Overall Performance ◽  
Process Uniformity ◽  
Transient Thermal

ABSTRACTRapid thermal oxidation (RTO) of Si using transient linearly-ramped-temperature saw-toothed (LRT-ST) and triangular (LRT-TA) thermal cycles has been examined through evaluations of the process uniformity, slip dislocation patterns, and electrical characteristics of MOS devices. The strong effects of the thermal cycle parameters on process uniformity and slips indicate that the overall performance of an RTP tool must be specified both under the steady-state and transient thermal cycles. The electrical characteristics of MOS devices with LRT-grown gate oxides are comparable to those for devices with oxides grown by the trapezoidal thermal cycles.

Electrical characteristics of ultrathin oxynitride gate dielectric prepared by rapid thermal oxidation of Si in N2O

1990 ◽  
Vol 57 (10) ◽  
pp. 1010-1011 ◽  
Author(s):  
Hyunsang Hwang ◽  
Wenchi Ting ◽  
Bikas Maiti ◽  
Dim‐Lee Kwong ◽  
Jack Lee
Keyword(s):  
Thermal Oxidation ◽  
Gate Dielectric ◽  
Electrical Characteristics ◽  
Rapid Thermal Oxidation

Comparative Studies of Gate Oxides Using Thermal, Stacked Gate, and Rapid Thermal Oxidation

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Chittipeddi ◽  
P. K. Roy ◽  
V. C. Kannan ◽  
R. Singh ◽  
C. M. Dziuba
Keyword(s):  
Thermal Oxidation ◽  
Defect Density ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Rapid Thermal Oxidation ◽  
Transmission Electron ◽  
Lattice Images ◽  
Flatband Voltage

AbstractIn this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

2000 ◽  
Vol 654 ◽  
Author(s):  
X. Duan ◽  
K. Kisslinger ◽  
L. Mayes ◽  
S. Ruby ◽  
J. Barrett
Keyword(s):  
Electron Microscopy ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Atomic Level ◽  
Electrical Performance ◽  
Interface Morphology ◽  
Gate Oxides ◽  
Mos Devices ◽  
Transmission Electron ◽  
The Impact

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

High Channel Mobility in P-Channel MOSFETs Fabricated on 4H-SiC (0001) and Non-Basal Faces

2009 ◽  
Vol 615-617 ◽  
pp. 789-792
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Thermal Oxidation ◽  
Interface State ◽  
Original Method ◽  
State Density ◽  
Interface State Density ◽  
Gate Oxides ◽  
Channel Mobility ◽  
Mos Devices

P-channel MOSFETs have been fabricated on 4H-SiC (0001) face as well as on 4H-SiC (03-38) and (11-20) faces. The gate oxides were formed by thermal oxidation in dry N2O ambient, which is widely accepted to improve the performance of n-channel SiC MOSFETs. The p-channel SiC MOSFETs with N2O-grown oxides on 4H-SiC (0001), (03-38), and (11-20) faces show a channel mobility of 7 cm2/Vs, 11 cm2/Vs, and 17 cm2/Vs, respectively. From the quasi-static C-V curves measured by using gate-controlled diodes, the interface state density was calculated by an original method. The interface state density was the lowest at the SiO2/4H-SiC (03-38) interface (about 1x1012 cm-2eV-1 at EV + 0.2 eV). The authors have applied deposited oxides to the 4H-SiC p-channel MOSFETs. The (0001), (03-38), and (11-20) MOSFETs with deposited oxides exhibit a channel mobility of 10 cm2/Vs, 13 cm2/Vs, and 17 cm2/Vs, respectively. The deposited oxides are one of effective approaches to improve both n-channel and p-channel 4H-SiC MOS devices.

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