Comparative Studies of Gate Oxides Using Thermal, Stacked Gate, and Rapid Thermal Oxidation

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Chittipeddi ◽  
P. K. Roy ◽  
V. C. Kannan ◽  
R. Singh ◽  
C. M. Dziuba
Keyword(s):  
Thermal Oxidation ◽  
Defect Density ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Rapid Thermal Oxidation ◽  
Transmission Electron ◽  
Lattice Images ◽  
Flatband Voltage

AbstractIn this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.

Influence of HCL on Rapid Thermal Oxides

1996 ◽  
Vol 429 ◽  
Author(s):  
G. A. Hames ◽  
S. E. Beck ◽  
A. G. Gilicinski ◽  
W. K. Henson ◽  
J. J. Wortman
Keyword(s):  
Thermal Oxidation ◽  
Gate Oxide ◽  
Surface Roughening ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Force Microscopy ◽  
Rapid Thermal Oxidation ◽  
Atomic Force ◽  
Secondary Ion

AbstractThe influence of HCl on the quality of gate oxides grown by rapid thermal oxidation has been investigated. HCl was added to oxidation ambient for some rapid thermal oxides while for others the silicon surface was annealed in a partial HCl ambient prior to rapid thermal oxidation. Improvements in gate oxide integrity were monitored on MOS capacitors and MOSFET devices by I-V and C-V testing. The levels of chlorine incorporated in the oxide from the addition of HCl to the process was measured by secondary ion mass spectroscopy. Atomic force microscopy was performed to measure surface roughening during HCl pre-oxidation treatments.

How Small Is Too Small ? Understanding The Electronic Structure Of Atomic-Scale Transistors

1999 ◽  
Vol 5 (S2) ◽  
pp. 120-121
Author(s):  
D. A. Muller ◽  
T. Sorsch ◽  
S. Moccio ◽  
F. H. Baumann ◽  
K. Evans-Lutterodt ◽  
...  
Keyword(s):  
Electronic Structure ◽  
Electrical Properties ◽  
Thermal Oxidation ◽  
Electronic Devices ◽  
Local Environment ◽  
Gate Oxide ◽  
Atomic Scale ◽  
Gate Oxides ◽  
Bulk Properties ◽  
Commercial Use

The transistors planned for commercial use ten years from now in many electronic devices will have gate lengths shorter than 130 atoms, gate oxides thinner than 1.2 nm of SiO2 and clock speeds in excess of 10 GHz. It is now technologically possible to produce such transistors with gate oxides only 5 silicon atoms thick[l]. Since at least two of those 5 atoms are not in a local environment similar to either bulk Si or bulk SiO2, the properties of the interface are responsible for a significant fraction of the “bulk” properties of the gate oxide. However the physical (and especially their electrical) properties of the interfacial atoms are very different from .bulk Si or bulk SiO2. Further, roughness on an atomic scale can alter the leakage current by orders of magnitude.In our studies of such devices, we found that thermal oxidation tends to produce Si/SiO2 interfaces with 0.1-0.2 nm rms roughness.

scholarly journals Influence of Low Temperature-Grown GaAs on Lateral Thermal Oxidation of Al0.98Ga0.02As

2000 ◽  
Vol 623 ◽  
Author(s):  
J. C. Ferrer ◽  
Z. Liliental-Weber ◽  
H. Reese ◽  
Y.J. Chiu ◽  
E. Hu
Keyword(s):  
Low Temperature ◽  
Thermal Oxidation ◽  
Oxidation Process ◽  
Gaas Layer ◽  
Transmission Electron ◽  
Low Temperature Gaas ◽  
Reference Samples ◽  
Thermal Oxidation Process ◽  
Low Temperature Grown Gaas

AbstractThe lateral thermal oxidation process of Al0.98Ga0.02As layers has been studied by transmission electron microscopy. Growing a low-temperature GaAs layer below the Al0.98Ga0.02As has been shown to result in better quality of the oxide/GaAs interfaces compared to reference samples. While the later have As precipitation above and below the oxide layer and roughness and voids at the oxide/GaAs interface, the structures with low-temperature have less As precipitation and develop interfaces without voids. These results are explained in terms of the diffusion of the As toward the low temperature layer. The effect of the addition of a Si02 cap layer is also discussed.

Ge Growth on Nanostructured Silicon Surfaces

2005 ◽  
Vol 862 ◽  
Author(s):  
Ganesh Vanamu ◽  
Abhaya K. Datye ◽  
Saleem H. Zaidi
Keyword(s):  
Electron Microscopy ◽  
Dislocation Density ◽  
Full Width Half Maximum ◽  
Defect Density ◽  
Chemical Vapor ◽  
Silicon Surfaces ◽  
X Ray Diffraction ◽  
Etch Pit ◽  
Transmission Electron

AbstractWe report highest quality Ge epilayers on nanoscale patterned Si structures. 100% Ge films of 10 μm are deposited using chemical vapor deposition. The quality of Ge layers was examined using scanning electron microscopy (SEM), transmission electron microscopy (TEM), and high-resolution x-ray diffraction (HRXRD) measurements. The defect density was evaluated using etch pit density measurements. We have obtained lowest dislocation density (5×105 cm-2) Ge films on the nanopatterned Si structures. The full width half maximum peaks of the reciprocal space maps of Ge epilayers on the nanopatterned Si showed 93 arc sec. We were able to get rid of the crosshatch pattern on the Ge surface grown on the nanopatterned Si. We also showed that there is a significant improvement of the quality of the Ge epilayers in the nanopatterned Si compared to an unpatterned Si. We observed nearly three-order magnitude decrease in the dislocation density in the patterned compared to the unpatterned structures. The Ge epilayer in the patterned Si has a dislocation density of 5×105 cm-2 as compared to 6×108 cm-2 for unpatterned Si.

A Comparison of Active Near-Interface Traps in Nitrided and As-Grown Gate Oxides by the Direct Measurement Technique

2020 ◽  
Vol 1004 ◽  
pp. 635-641
Author(s):  
Peyush Pande ◽  
Sima Dimitrijev ◽  
Daniel Haasmann ◽  
Hamid Amini Moghadam ◽  
Philip Tanner ◽  
...  
Keyword(s):  
Nitric Oxide ◽  
Comparative Analysis ◽  
Direct Measurement ◽  
Measurement Technique ◽  
Measurement Method ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Direct Measurement Method

This paper presents a comparative analysis of the electrically active near-interface traps, energetically located above the bottom of conduction band. Two different samples of N-type SiC MOS capacitors were fabricated with gate oxides grown in (1) dry O2 (as-grown) and (2) dry O2 annealed in nitric oxide (nitride). Measurements performed by the direct measurement method revealed that the traps located further away from the SiO2/SiC interface are removed by nitridation. A spatially localized behaviour of NITs is observed only in the nitrided gate oxide but not in the as-grown gate oxide.

Influence of Pre-Gate Cleaning ON Si/SiO2 Interface and Electrical Performance of Cmos Gate Oxide

2000 ◽  
Vol 654 ◽  
Author(s):  
X. Duan ◽  
K. Kisslinger ◽  
L. Mayes ◽  
S. Ruby ◽  
J. Barrett
Keyword(s):  
Electron Microscopy ◽  
Gate Dielectrics ◽  
Gate Oxide ◽  
Atomic Level ◽  
Electrical Performance ◽  
Interface Morphology ◽  
Gate Oxides ◽  
Mos Devices ◽  
Transmission Electron ◽  
The Impact

AbstractThe Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

Influence of Threading Dislocations on Lifetime of Gate Thermal Oxide

2012 ◽  
Vol 717-720 ◽  
pp. 477-480 ◽  
Author(s):  
Kensaku Yamamoto ◽  
M. Nagaya ◽  
H. Watanabe ◽  
E. Okuno ◽  
T. Yamamoto ◽  
...  
Keyword(s):  
Dielectric Breakdown ◽  
Gate Oxide ◽  
Crystal Defects ◽  
Gate Oxides ◽  
Time Dependent Dielectric Breakdown ◽  
Transmission Electron ◽  
Thermal Oxide ◽  
Order Of Magnitude ◽  
The Relationship ◽  
Exact Relationship

The reliability of gate oxides is a fundamental issue for realizing SiC MOSFETs. Many reports said that crystal defects shorten the lifetime of the gate oxide. And, epi defects, the basal plane dislocations and threading screw dislocations (TSD) are considered killer defects. However, because of the high TSD density of commercial SiC wafers, the exact relationship between other kinds of dislocations with lifetime has not been revealed. On the other hand, RAF wafers that we developed have low TSD density, so it is easy to evaluate the relationship between other kinds of dislocations and lifetime. By using RAF wafers, in this study, we clarified the relationship between the lifetime of the gate oxide and crystal defects. We fabricated MOS diodes and measured their lifetimes by TDDB (Time Dependent Dielectric Breakdown) measurement. The breakdown points were defined by the photo-emission method. Finally, we classified the defects by TEM (Transmission Electron Microscopy). As the results, it was clarified that threading edge dislocation (TED) decreases the lifetime as does TSD, which earlier reports said. The lifetime of the gate oxide area, in which a TED is included, was shorter by one order of magnitude than a wear-out breakdown. And, the TSD was two orders.

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