Radiation Response of Thin Oxides Grown By Rapid Thermal Oxidation and Rapid Thermal Annealing Techniques

1987 ◽  
Vol 105 ◽  
Author(s):  
W. K. Schubert ◽  
C. H. Seager
Keyword(s):  
Thermal Oxidation ◽  
High Frequency ◽  
Interface State ◽  
Oxide Semiconductor ◽  
Radiation Response ◽  
Mos Capacitors ◽  
Rapid Thermal Oxidation ◽  
Hole Trapping ◽  
Radiation Induced ◽  
State Creation

AbstractHigh quality, 20 to 30 nm thick SiO2 films were grown using rapid thermal oxidation techniques. Metal-oxide-semiconductor (MOS) capacitors formed with these oxides were characterized electrically using low and high frequency capacitance measurements. The effects of post oxidation annealing (POA) ambient, temperature and duration on the initial oxide properties and the radiation response of the MOS capacitors were determined. The addition of a small amount of O2 to the POA ambient significantly reduced the radiation induced hole trapping and interface state creation, particularly for the higher POA temperatures. In addition, annealing and reirradiation experiments were carried out and showed that both the trapped charge and interface state buildup were completely reversible after anneals at 400°C. This repeatability argues against interface state creation models which involve irreversible changes in the atomic arrangements near the interface.

Rapid Thermal Oxidation of Lightly Doped Silicon in N2O

1994 ◽  
Vol 342 ◽  
Author(s):  
S.C. Sun ◽  
L.S. Wang ◽  
F.L. Yeh ◽  
T.S. Lai ◽  
Y.H. Lin
Keyword(s):  
Growth Rate ◽  
Thermal Oxidation ◽  
Charge Trapping ◽  
Interface State ◽  
Constant Current ◽  
Mos Capacitor ◽  
Rapid Thermal Oxidation ◽  
Doped Silicon ◽  
State Generation ◽  
First Time

ABSTRACTIn this paper, a detailed study is presented for the growth kinetics of rapid thermal oxidation of lightly-doped silicon in N2O and O2 on (100), (110), and (111) oriented substrates. It was found that (110)-oriented Si has the highest growth rate in both N2O and dry O2, and (100) Si has the lowest rate. There is no “crossover” on the growth rate of rapid thermal N2O oxidation between (110) Si and (111) Si as compared to oxides grown in furnace N2O. Pressure dependence of rapid thermal N2O oxidation is reported for the first time. MOS capacitor results show that the low-pressure (40 Torr) N2O-grown oxides have much less interface state generation and charge trapping under constant current stress as compared to oxides grown in either 760 Torr N2O or O2 ambient.

Effect of Interfacial Localization of Phosphorus on Electrical Properties and Reliability of 4H-SiC MOS Devices

2013 ◽  
Vol 740-742 ◽  
pp. 695-698 ◽  
Author(s):  
Tsuyoshi Akagi ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
State Density ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Device Properties ◽  
Phosphorus Doped ◽  
Post Deposition ◽  
Mos Device

Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO2/SiC interface were fabricated on 4H-SiC by direct POCl3treatment followed by SiO2deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

Processing and Characterization of MOS Capacitors Fabricated on 2°-Off Axis 4H-SiC Epilayers

2016 ◽  
Vol 858 ◽  
pp. 663-666
Author(s):  
Marilena Vivona ◽  
Patrick Fiorenza ◽  
Tomasz Sledziewski ◽  
Alexandra Gkanatsiou ◽  
Michael Krieger ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Interface State ◽  
State Density ◽  
Metal Oxide Semiconductor ◽  
Interface State Density ◽  
Device Fabrication ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Oxide Breakdown

In this work, the electrical properties of SiO2/SiC interfaces onto a 2°-off axis 4H-SiC layer were studied and validated through the processing and characterization of metal-oxide-semiconductor (MOS) capacitors. The electrical analyses on the MOS capacitors gave an interface state density in the low 1×1012 eV-1cm-2 range, which results comparable to the standard 4°-off-axis 4H-SiC, currently used for device fabrication. From Fowler-Nordheim analysis and breakdown measurements, a barrier height of 2.9 eV and an oxide breakdown of 10.3 MV/cm were determined. The results demonstrate the maturity of the 2°-off axis material and pave the way for the fabrication of 4H-SiC MOSFET devices on this misorientation angle.

High Frequency Inversion Capacitance Measurements for 6H-SiC n-MOS Capacitors from 450 to 600 °C

2008 ◽  
Vol 600-603 ◽  
pp. 739-742 ◽  
Author(s):  
Ruby N. Ghosh ◽  
Reza Loloee ◽  
Tamara Isaacs-Smith ◽  
John R. Williams
Keyword(s):  
High Frequency ◽  
Operating Conditions ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Physical Processes ◽  
Large Area ◽  
Thermal Generation ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Minority Carriers

The operation of metal-oxide-semiconductor (MOS) devices based on the semiconductor SiC in high temperature environments above 300 °C requires an understanding of the physical processes in these capacitor structures under operating conditions. In this study we have focused on the regime of inversion biasing, where the electrical characteristics of the device are dominated by minority carriers. We report on the direct observation of the high frequency inversion capacitance due to thermal generation of holes in 6H-SiC n-MOS capacitors between 450 and 600 °C by monitoring the 1MHz C-V characteristics of large area, 1000 μm diameter, capacitors in the dark. Our experimental results are consistent with a first order calculation based on the delta depletion approximation.

Comparative Studies of Gate Oxides Using Thermal, Stacked Gate, and Rapid Thermal Oxidation

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Chittipeddi ◽  
P. K. Roy ◽  
V. C. Kannan ◽  
R. Singh ◽  
C. M. Dziuba
Keyword(s):  
Thermal Oxidation ◽  
Defect Density ◽  
Gate Oxide ◽  
Gate Oxides ◽  
Mos Capacitors ◽  
Rapid Thermal Oxidation ◽  
Transmission Electron ◽  
Lattice Images ◽  
Flatband Voltage

AbstractIn this paper we report on the quality of gate oxides obtained using three different oxidation techniques, namely thermal oxidation, rapid thermal oxidation and stacked gate oxidation. We report on the oxide thicknesses, the flatband voltage, threshold voltage, and QSS/Q values for MOS capacitors fabricated using these three techniques. We also fabricated MOSFET's using thermal oxides and stacked gate oxides, and find that the stacked gate oxides have a lower gate oxide defect density. Lattice images have also been obtained for the Si/SiO2 interface using transmission electron microscopy (TEM). We find that stacked oxide synthesis results in lower stresses and asperities at the interface relative to thermal and rapid thermal oxidation.

scholarly journals Creation of Interface States at the Silicon/Silicon Dioxide Interface by UV Light Without Hole Trapping

1989 ◽  
Vol 148 ◽  
Author(s):  
W. K. Schubert ◽  
C. H. Seager ◽  
K. L. Brower
Keyword(s):  
Silicon Dioxide ◽  
Silicon Substrate ◽  
Uv Light ◽  
Interface States ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Hole Trapping ◽  
Creation Rate ◽  
Silicon Silicon

ABSTRACTPhotoinjection of electrons into silicon dioxide in metal-oxide-semiconductor (MOS) capacitors with 3.5 eV light is shown to create interface states with no apparent hole trapping precursor. The creation rate of these interface states depends strongly upon whether injection is from the gate metal or the silicon substrate, and on the forming gas annealing sequence used to passivate growth-induced interface states. A mechanism involving electron-induced release of hydrogen in the oxide is consistent with some aspects of the data.

Systematic Investigation of Interface Properties in 4H-SiC MOS Structures Prepared by Over-Oxidation of Ion-Implanted Substrates

2010 ◽  
Vol 645-648 ◽  
pp. 495-498 ◽  
Author(s):  
Dai Okamoto ◽  
Hiroshi Yano ◽  
Tomoaki Hatayama ◽  
Takashi Fuyuki
Keyword(s):  
Interface State ◽  
Systematic Investigation ◽  
Implantation Dose ◽  
State Density ◽  
Interface State Density ◽  
Oxide Semiconductor ◽  
Conduction Band Edge ◽  
Strong Reduction ◽  
Mos Capacitors ◽  
Mos Structures

A change in the interface state density in 4H-SiC metal–oxide–semiconductor (MOS) structures by incorporation of various elements was systematically investigated. B, N, F, Al, P, and Cl ions were implanted prior to the oxidation and introduced at the SiO2/SiC interface by subsequent thermal oxidation. Interface state density near the conduction band edge for Al-, B-, F-, and Cl-implanted MOS capacitors increased with implantation dose. On the other hand, a strong reduction of the interface state density was observed for N- and P-implanted samples when the implantation dose was larger than 5.0 × 1012 cm−2. It was found that the interface state density can be reduced by P as well as N.

Thin Oxide Defects Resulting from Plasma Induced Wafer Charging

1992 ◽  
Vol 262 ◽  
Author(s):  
Sychyi Fang ◽  
James P. McVittie
Keyword(s):  
Negative Charge ◽  
Interface State ◽  
State Density ◽  
Interface State Density ◽  
Mos Capacitors ◽  
Antenna Structure ◽  
Hole Trapping ◽  
Breakdown Mechanism ◽  
Polarity Effects ◽  
Wafer Charging

ABSTRACTEEPROM charge monitors reveal that an O2 plasma induces a negative charge which peaks at the wafer center for the asher used. The charge damage to small gate area MOS capacitors is investigated by using “antenna” structure. The post plasma interface state density increases with increasing antenna size and varies by two orders of magnitude. A hole trapping induced breakdown mechanism during plasma charging is supported by new experimental evidence such as the annealing and polarity effects of charge-to-breakdown and tunneling currents. Where stressing has not being severe, these hole traps are annealable at T > 650°C, while in severely stressed areas early breakdown occurs which is not annealable.

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