scholarly journals Creation of Interface States at the Silicon/Silicon Dioxide Interface by UV Light Without Hole Trapping

1989 ◽  
Vol 148 ◽  
Author(s):  
W. K. Schubert ◽  
C. H. Seager ◽  
K. L. Brower
Keyword(s):  
Silicon Dioxide ◽  
Silicon Substrate ◽  
Uv Light ◽  
Interface States ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Hole Trapping ◽  
Creation Rate ◽  
Silicon Silicon

ABSTRACTPhotoinjection of electrons into silicon dioxide in metal-oxide-semiconductor (MOS) capacitors with 3.5 eV light is shown to create interface states with no apparent hole trapping precursor. The creation rate of these interface states depends strongly upon whether injection is from the gate metal or the silicon substrate, and on the forming gas annealing sequence used to passivate growth-induced interface states. A mechanism involving electron-induced release of hydrogen in the oxide is consistent with some aspects of the data.

Near-interface Traps in n-type SiO2/SiC MOS Capacitors from Energy-resolved CCDLTS

2010 ◽  
Vol 1246 ◽  
Author(s):  
Alberto F Basile ◽  
Sarit Dhar ◽  
John Rozen ◽  
Xudong Chen ◽  
John Williams ◽  
...  
Keyword(s):  
Silicon Dioxide ◽  
Electron Emission ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Emission Rates ◽  
Mos Capacitors ◽  
Transient Spectroscopy

AbstractSilicon Carbide (SiC) Metal-Oxide-Semiconductor (MOS) capacitors, having different nitridation times, were characterized by means of Constant Capacitance Deep Level Transient Spectroscopy (CCDLTS). Electron emission was investigated with respect to the temperature dependence of emission rates and the amplitude of the signal as a function of the filling voltage. The comparison between the emission activation energies of the dominant CCDLTS peaks and the filling voltages, led to the conclusion that the dominant trapping behavior originates in the Silicon-dioxide (SiO2) layer. Moreover, a model of electron capture via tunneling can explain the dependence of the CCDLTS signal on increasing filling voltage.

Effect of Increased Oxide Hole Trap Density due to Nitrogen Incorporation at the SiO2/SiC Interface on F-N Current Degradation

2011 ◽  
Vol 679-680 ◽  
pp. 382-385 ◽  
Author(s):  
Christian Strenger ◽  
Anton J. Bauer ◽  
Heiner Ryssel
Keyword(s):  
Silicon Carbide ◽  
Silicon Dioxide ◽  
Gate Dielectrics ◽  
Charge Trapping ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Hole Trap ◽  
Mos Capacitors ◽  
Nitrogen Incorporation ◽  
Oxide Trapped Charge

Metal-oxide-semiconductor (MOS) capacitors were formed on 4H-silicon carbide (SiC) using thermally grown silicon dioxide (SiO2) as gate dielectrics, both with and without nitrogen incorporation within the oxide. The field dependence of the charge trapping properties of these structures was analyzed and linked to the observed Fowler-Nordheim current degradation. Furthermore, first considerations were presented that indicate an electron impact emission induced generation of positive oxide trapped charge.

Trapping States in SiO2/GaN MOS Capacitors Fabricated on Recessed AlGaN/GaN Heterostructures

2016 ◽  
Vol 858 ◽  
pp. 1178-1181
Author(s):  
Patrick Fiorenza ◽  
Giuseppe Greco ◽  
Ferdinando Iucolano ◽  
Antonino Parisi ◽  
Santo Reina ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Response Time ◽  
Interface States ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Post Deposition Annealing ◽  
Mos Capacitors ◽  
Hydrogen Incorporation ◽  
Characteristic Response ◽  
Post Deposition

In this work, the different nature of trapping states in metal-oxide-semiconductor (MOS) capacitors fabricated on recessed AlGaN/GaN heterostructures has been investigated. In particular, the origin of both fast and slow states has been elucidated by frequency dependent conductance measurements. Using post deposition annealing in forming gas, which is known to induce hydrogen incorporation at the interface, allowed to ascribe the fast traps (with characteristic response time in the range of 5–50 μs) to SiO2/GaN interface states and the slow traps (50–100 μs) to “border traps” located few nanometers inside the SiO2 layer. The results can be useful to predict the behavior of GaN switching devices, like hybrid MOSHEMTs.

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