Influence of size variation on the strain distribution in YSZ membranes on Si substrates

2013 ◽  
Vol 1495 ◽  
Author(s):  
Florian Kuhl ◽  
Markus Piechotka ◽  
Daniel Reppin ◽  
Torsten Henning ◽  
Juergen Janek ◽  
...  
Keyword(s):  
Solid Oxide Fuel Cells ◽  
Electric Propulsion ◽  
Size Variation ◽  
Silicon Substrates ◽  
Si Substrate ◽  
Stabilized Zirconia ◽  
Free Standing ◽  
Si Substrates ◽  
Radio Frequency Sputtering ◽  
Wet Chemical

ABSTRACTThe oxygen conductor yttria-stabilized-zirconia (YSZ) is widely used in miniaturized solid oxide fuel cells (µSOFC) and may be suitable for solid state ion emitter applications e.g. as miniaturized ion engines for electric propulsion. Since the YSZ films are not completely free of stress during the growth, cracks in fabricated free-standing membranes are often observed.YSZ thin films were deposited on silicon substrates by radio frequency sputtering. Free-standing YSZ membranes were fabricated by partially removing the Si substrate by anisotropic wet-chemical etching using different masking patterns defined by electron beam lithography. We show how different sizes and etching conditions influence the strain in the fabricated membranes. To characterize these membranes we used optical microscopy and scanning electron microscopy.

Constrained and Non-Constrained Sintering of Plasma-Sprayed Zirconia Based Electrolytes for SOFCs

2010 ◽  
Vol 65 ◽  
pp. 263-268 ◽  
Author(s):  
Claudia Christenn ◽  
Syed Asif Ansar
Keyword(s):  
Solid Oxide Fuel Cells ◽  
Atmospheric Plasma Spraying ◽  
Solid Oxide ◽  
Yttria Stabilized Zirconia ◽  
Atmospheric Plasma ◽  
Oxide Fuel ◽  
Microstructure Development ◽  
Stabilized Zirconia ◽  
Free Standing ◽  
Plasma Sprayed

Electrolyte layers for solid oxide fuel cells (SOFCs) consisting typically of yttria-stabilized zirconia were prepared using atmospheric plasma spraying in a first step and sintered in a second one. The influence of particle size on sintering kinetics and microstructure development was analyzed by comparison of nanostructured and conventional YSZ layers. Sintering of free-standing coatings differ significantly from that of coatings on substrates.

scholarly journals O-Band Emitting InAs Quantum Dots Grown by MOCVD on a 300 mm Ge-Buffered Si (001) Substrate

Nanomaterials ◽  
2020 ◽  
Vol 10 (12) ◽  
pp. 2450
Author(s):  
Oumaima Abouzaid ◽  
Hussein Mehdi ◽  
Mickael Martin ◽  
Jérémy Moeyaert ◽  
Bassem Salem ◽  
...  
Keyword(s):  
Quantum Dots ◽  
Chemical Vapor ◽  
Lattice Parameter ◽  
Organic Chemical ◽  
Silicon Substrates ◽  
Wafer Level ◽  
Si Substrate ◽  
Si Substrates ◽  
Transmission Electron ◽  
Metal Organic

The epitaxy of III-V semiconductors on silicon substrates remains challenging because of lattice parameter and material polarity differences. In this work, we report on the Metal Organic Chemical Vapor Deposition (MOCVD) and characterization of InAs/GaAs Quantum Dots (QDs) epitaxially grown on quasi-nominal 300 mm Ge/Si(001) and GaAs(001) substrates. QD properties were studied by Atomic Force Microscopy (AFM) and Photoluminescence (PL) spectroscopy. A wafer level µPL mapping of the entire 300 mm Ge/Si substrate shows the homogeneity of the three-stacked InAs QDs emitting at 1.30 ± 0.04 µm at room temperature. The correlation between PL spectroscopy and numerical modeling revealed, in accordance with transmission electron microscopy images, that buried QDs had a truncated pyramidal shape with base sides and heights around 29 and 4 nm, respectively. InAs QDs on Ge/Si substrate had the same shape as QDs on GaAs substrates, with a slightly increased size and reduced luminescence intensity. Our results suggest that 1.3 μm emitting InAs QDs quantum dots can be successfully grown on CMOS compatible Ge/Si substrates.

OPTICAL PROPERTIES OF Ge NANOWIRES GROWN ON SILICON (100) AND (111) SUBSTRATES

2004 ◽  
Vol 832 ◽  
Author(s):  
V. Sharma ◽  
B. V. Kamenev ◽  
L. Tsybeskov ◽  
T. I. Kamins
Keyword(s):  
Vapor Deposition ◽  
Chemical Vapor ◽  
Growth Direction ◽  
Silicon Substrates ◽  
Si Substrate ◽  
Vapor Liquid Solid ◽  
Preferential Growth ◽  
Intensity Dependence ◽  
Si Substrates ◽  
Preferential Growth Direction

ABSTRACTIn this paper, we report Raman Scattering (RS) and photoluminescence (PL) measurements of Ge nanowires (NWs) grown via vapor-liquid-solid (VLS) using chemical vapor deposition silicon substrates consisting of (100) and (111) crystallographic orientations. Ge NWs grown are ∼40 nm in diameter, approximately a micrometer in length, and a sharp narrow Raman peak at ∼300 cm−1 indicates single crystal quality. An absence of SiGe peak in the Raman spectra indicates that SiGe interdiffusion is insignificant for the NW volume. Low temperature PL-intensity-dependence spectra indicate that the observed emission originates at the Ge NW – Si substrate interface, where SiGe intermixing has been detected. This interface is formed differently for (111) and (100) oriented Si substrates due to the <111> preferential growth direction of Ge NWs.

Schottky Diode Characteristics of CVD—Grown β —SiC Epitaxial Films on (n11) Silicon Substrates ( n= 1,3,4,5,6 ).

1988 ◽  
Vol 116 ◽  
Author(s):  
Yoshihisa Fujii ◽  
Atsuko Ogura ◽  
Katsuki Furukawa ◽  
Mitsuhiro Shigeta ◽  
Akira Suzuki ◽  
...  
Keyword(s):  
Schottky Diode ◽  
Schottky Diodes ◽  
Epitaxial Films ◽  
Silicon Substrates ◽  
Si Substrate ◽  
Leakage Currents ◽  
Substrate Orientation ◽  
Si Substrates ◽  
Barrier Heights ◽  
Sic Films

AbstractSchottky barrier contacts have been made on CVD—grown β - SiC on Si substrates, and their C—V and I—V characteristics are measured. Dependence of the Schottky characteristics on Si substrate orientation ((n11),(n=1,3,4,5,6), and (100)) is examined. The Schottky diodes of the β-SiC films on Si (611), Si(411), and Si (111) show excellent characteristics compared with the conventional Schottky diodes using Si(100) substrates. That is, reverse leakage currents are small, ideality factors are close to unity, and barrier heights are larger.

Formation Of Stacking Fault Tetrahedra During Epitaxial Growth of Silicon and Germanium-Silicon Layers on {111} Silicon Substrates

1985 ◽  
Vol 54 ◽  
Author(s):  
D. Brasen ◽  
S. Nakahara ◽  
J. C. Bean
Keyword(s):  
Molecular Beam ◽  
Stacking Fault ◽  
Silicon Substrates ◽  
Si Substrate ◽  
Si Substrates ◽  
Transmission Electron ◽  
Stacking Fault Tetrahedra ◽  
Local Stresses ◽  
Silicon And Germanium ◽  
Germanium Silicon

ABSTRACTTransmission electron microscopy was used to characterize defects formed in silicon (Si) and germanium-silicon (Ge-Si) alloy layers grown sequentially by molecular-beam epitaxy (MBE) on {111} Si substrates. Stacking fault tetrahedra (SFT) were found to form in these epitaxial layers. In addition, the apex of the SFT are seen to be pointing down toward the Si substrate, with most of the SFT tips converging exactly at the Si/Si and the Ge-Si/Si interfaces. Diffraction contrast experiments using various two-beam conditions have shown that the stacking faults bounding the SFT are of intrinsic (vacancy) type. In the case of a Si layer on the Si substrate, it is reasoned that the SFT are caused by impurities on the surface of the Si substrate prior to deposition. However, in the Ge-Si layer, it is believed that the formation of the S FT is due to local stresses caused by the structural ordering/phase separation of the Ge atoms.

A novel 3C-SiC on Si power Schottky diode design and modelling

2014 ◽  
Vol 1693 ◽  
Author(s):  
Fan Li ◽  
Yogesh K. Sharma ◽  
Craig A. Fisher ◽  
Michael R. Jennings ◽  
Philip A. Mawby
Keyword(s):  
Finite Element ◽  
Electric Vehicles ◽  
Schottky Diode ◽  
Physical Models ◽  
Silicon Substrates ◽  
Si Substrate ◽  
Power Devices ◽  
Large Area ◽  
Free Standing ◽  
Economical Choice

ABSTRACTAlthough 3C-SiC has a narrower bandgap than 4H-SiC, it is the only SiC polytype that can be grown directly over large area silicon substrates. It has the potential to provide a more economical choice than 4H-SiC for intermediate power devices, such as inverters for electric vehicles. To fabricate a vertical device on 3C-SiC, the Si substrate is usually removed either by etching or polishing. Neither of these processes is economical nor efficient. In this paper we propose a lateral Schottky diode design for 3C-SiC on Si structure. 2D finite element simulations using ATLAS showed that a breakdown voltage beyond 1200 V can be achieved with a 4 μm thick epilayer. Physical models used for 3C-SiC/Si power devices simulations are introduced. Advantages of lateral 3C-SiC/Si diodes over free standing 3C-SiC are also discussed.

Electron Energy Analysis of Germanium and Silica Layers on Silicon Substrates

1975 ◽  
Vol 33 ◽  
pp. 96-97
Author(s):  
R. W. Ditchfield ◽  
A. G. Cullis
Keyword(s):  
Epitaxial Growth ◽  
Electron Energy ◽  
Silicon Substrates ◽  
Secondary Phases ◽  
Si Substrates ◽  
Transmission Electron ◽  
Layer Structures ◽  
Si Films ◽  
Electron Energy Loss ◽  
Growth Centres

An energy analyzing transmission electron microscope of the Möllenstedt type was used to measure the electron energy loss spectra given by various layer structures to a spatial resolution of 100Å. The technique is an important, method of microanalysis and has been used to identify secondary phases in alloys and impurity particles incorporated into epitaxial Si films.Layers Formed by the Epitaxial Growth of Ge on Si Substrates Following studies of the epitaxial growth of Ge on (111) Si substrates by vacuum evaporation, it was important to investigate the possible mixing of these two elements in the grown layers. These layers consisted of separate growth centres which were often triangular and oriented in the same sense, as shown in Fig. 1.

scholarly journals Surface Texturing of Si with Periodically Arrayed Oblique Nanopillars to Achieve Antireflection

Materials ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 380
Author(s):  
Jun-Hyun Kim ◽  
Sanghyun You ◽  
Chang-Koo Kim
Keyword(s):  
Aspect Ratio ◽  
Plasma Etching ◽  
Surface Texturing ◽  
Light Reflection ◽  
Si Substrate ◽  
Weighted Mean ◽  
Optical Reflectance ◽  
Si Substrates ◽  
Aspect Ratios ◽  
Shadowing Effect

Si surfaces were texturized with periodically arrayed oblique nanopillars using slanted plasma etching, and their optical reflectance was measured. The weighted mean reflectance (Rw) of the nanopillar-arrayed Si substrate decreased monotonically with increasing angles of the nanopillars. This may have resulted from the increase in the aspect ratio of the trenches between the nanopillars at oblique angles due to the shadowing effect. When the aspect ratios of the trenches between the nanopillars at 0° (vertical) and 40° (oblique) were equal, the Rw of the Si substrates arrayed with nanopillars at 40° was lower than that at 0°. This study suggests that surface texturing of Si with oblique nanopillars reduces light reflection compared to using a conventional array of vertical nanopillars.

scholarly journals Formation and Evaluation of Silicon Substrate with Highly-Doped Porous Si Layers Formed by Metal-Assisted Chemical Etching

2021 ◽  
Vol 16 (1) ◽  
Author(s):  
Yijie Li ◽  
Nguyen Van Toan ◽  
Zhuqing Wang ◽  
Khairul Fadzli Bin Samat ◽  
Takahito Ono
Keyword(s):  
Electrical Conductivity ◽  
Seebeck Coefficient ◽  
Contact Resistance ◽  
Power Factor ◽  
Chemical Etching ◽  
Porous Si ◽  
Si Substrate ◽  
Si Substrates ◽  
Output Performance ◽  
Metal Assisted Chemical Etching

AbstractPorous silicon (Si) is a low thermal conductivity material, which has high potential for thermoelectric devices. However, low output performance of porous Si hinders the development of thermoelectric performance due to low electrical conductivity. The large contact resistance from nonlinear contact between porous Si and metal is one reason for the reduction of electrical conductivity. In this paper, p- and n-type porous Si were formed on Si substrate by metal-assisted chemical etching. To decrease contact resistance, p- and n-type spin on dopants are employed to dope an impurity element into p- and n-type porous Si surface, respectively. Compared to the Si substrate with undoped porous samples, ohmic contact can be obtained, and the electrical conductivity of doped p- and n-type porous Si can be improved to 1160 and 1390 S/m, respectively. Compared with the Si substrate, the special contact resistances for the doped p- and n-type porous Si layer decreases to 1.35 and 1.16 mΩ/cm2, respectively, by increasing the carrier concentration. However, the increase of the carrier concentration induces the decline of the Seebeck coefficient for p- and n-type Si substrates with doped porous Si samples to 491 and 480 μV/K, respectively. Power factor is related to the Seebeck coefficient and electrical conductivity of thermoelectric material, which is one vital factor that evaluates its output performance. Therefore, even though the Seebeck coefficient values of Si substrates with doped porous Si samples decrease, the doped porous Si layer can improve the power factor compared to undoped samples due to the enhancement of electrical conductivity, which facilitates its development for thermoelectric application.

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