Germanium Junctions for Beyond-Si Node Using Flash Lamp Annealing (FLA)

MRS Advances ◽  
2017 ◽  
Vol 2 (51) ◽  
pp. 2921-2926 ◽  
Author(s):  
H. Tanimura ◽  
H. Kawarazaki ◽  
K. Fuse ◽  
M. Abe ◽  
Y. Ito ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Carrier Concentration ◽  
Flash Lamp ◽  
Junction Depth ◽  
High Activation ◽  
Monolithically Integrated ◽  
Implantation Damage ◽  
Shallow Junctions ◽  
High Boron ◽  
Very High

ABSTRACTWe report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths (Xj) formed for the n+/p and p+/n junctions were 7.6 nm and 6.1 nm with sheet resistances (Rs) of 860 ohms/sq. and 704 ohms/sq., respectively. By reducing knocked-on oxygen during ion implantation in the n+/p junctions, Rs was decreased by between 5% and 15%. The lowest Rs observed was 235 ohms/sq. with a junction depth of 21.5 nm. Hall measurements clearly revealed that knocked-on oxygen degraded phosphorus activation (carrier concentration). In the p+/n Ge junctions, we show that ion implantation damage induced high boron activation. Using this technique, Rs can be reduced from 475 ohms/sq. to 349 ohms/sq. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices that can take us beyond Si technology.

scholarly journals Formation and Characterization of Shallow Junctions in GaAs Made by Ion Implantation and ms‐Range Flash Lamp Annealing

2018 ◽  
Vol 216 (8) ◽  
pp. 1800618
Author(s):  
Juanmei Duan ◽  
Mao Wang ◽  
Lasse Vines ◽  
Roman Böttger ◽  
Manfred Helm ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Flash Lamp ◽  
Shallow Junctions

Ultra Shallow Junctions Optimization with Non Doping Species Co-implantation

2006 ◽  
Vol 912 ◽  
Author(s):  
Nathalie Cagnat ◽  
Cyrille Laviron ◽  
Daniel Mathiot ◽  
Blandine Duriez ◽  
Julien Singer ◽  
...  
Keyword(s):  
Experimental Study ◽  
Integrated Circuits ◽  
Dopant Concentration ◽  
Junction Depth ◽  
Complex Interactions ◽  
Implantation Damage ◽  
Efficient Diffusion ◽  
Shallow Junctions ◽  
Light Ions ◽  
Ultra Shallow Junctions

AbstractThe permanent decrease of the transistor size to improve the performances of integrated circuits must be accompanied by a permanent decrease of the depth of the source-drain junctions. At the same time, in order to keep acceptable sheet resistance values, the dopant concentration in the source-drain areas has to be continuously increased. A possible technological way to meet the junction depth and abruptness requirements is to use co-implantation of non doping species with classical implantations, especially for light ions as B or P.In order to clarify the complex interactions occurring during these co-implantation processes, we have performed an extensive experimental study of the effect of Ge, F, N, C and their combinations on boron. A special interest was given to the overall integration issues. We will show that it is required to optimize the respective locations of co-implanted species with respect to the B profiles (more precisely the ion implantation damage locations), as well as the co-implanted species doses, to get an acceptable compromise between the efficient diffusion decrease required for the junction abruptness and depth, and a reasonable current leakages.

Formation of Cosi2-Shallow Junctions By Ion Beam Mixing and Rapid Thermal Annealing

1990 ◽  
Vol 181 ◽  
Author(s):  
L. Niewöhner ◽  
D. Depta
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Ion Beam ◽  
Dopant Distribution ◽  
Junction Depth ◽  
Ion Beam Mixing ◽  
Sem And Tem ◽  
Shallow Junctions

ABSTRACTFormation of CoSi2 using the technique of ion implantation through metal (ITM) and subsequent appropriate rapid thermal annealing is described. Silicide morphology is investigated by SEM and TEM. SIMS and RBS are used to determine dopant distribution and junction depth. Self-aligned CoSi2/n+p diodes produced in this technique are presented.

As and B Ion Implantation Through Mo and into Mo-Silicide Layers for Shallow Junction Formation

1989 ◽  
Vol 157 ◽  
Author(s):  
R. Angelucci ◽  
M. Merli ◽  
S. Solmi ◽  
A. Armigliato ◽  
E. Gabilli ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Carrier Concentration ◽  
Rapid Thermal Annealing ◽  
Current Density ◽  
Reverse Current ◽  
Concentration Profiles ◽  
Leakage Currents ◽  
Junction Formation ◽  
Shallow Junctions ◽  
Silicon Interface

ABSTRACTGood quality p+/n and n+/p shallow junctions (< 0.15 um) with reverse current density of few nA/cm2 and low contact resistivity (∼ 5×10–7 Ω cm2) have been fabricated by using Mo suicide and Rapid Thermal Annealing (RTA). The processes of implantation through Mo films and into MoSi2 layers have been comparatively analysed on the basis of SIMS and carrier concentration profiles, TEM observations and DLTS measurements. In the case of n+/p diodes fabricated by ITM technology slightly worse leakage currents have been observed, in spite of the better planarity of the silicide-silicon interface exhibited by these structures.

Temperature Dependent Current-Voltage Characteristics of TiSi2/n+/p-Si Shallow Junctions

1990 ◽  
Vol 181 ◽  
Author(s):  
Bhupen Shah ◽  
N.M. Ravindra
Keyword(s):  
Ion Implantation ◽  
Band Gap ◽  
Carrier Concentration ◽  
Temperature Dependent ◽  
Si Substrates ◽  
Current Voltage ◽  
Shallow Junctions ◽  
Current Voltage Characteristics ◽  
Band Gap Narrowing ◽  
Ti Films

ABSTRACTModelling of temperature dependent current-voltage characteristics of TiSi2/n+/p-Si shallow junctions has been presented here. The formation of shallow pn junctions, by ion implantation of As+ through Ti films evaporated on p-Si substrates has been performed in these experiments. The temperature dependent factors such as band gap narrowing, intrinsic carrier concentration, mobilities and diffusivities are considered in the model.

The Use of SiGe Barriers During the Formation of p+ Shallow Junctions by Ion Implantation

2004 ◽  
Vol 810 ◽  
Author(s):  
Phillip E. Thompson ◽  
Joe Bennett ◽  
Susan Felch
Keyword(s):  
Thermal Stability ◽  
High Temperature ◽  
Ion Implantation ◽  
Control Sample ◽  
Alloy Layer ◽  
Junction Depth ◽  
Effective Barrier ◽  
High Temperature Processes ◽  
Shallow Junctions ◽  
Thermal Stability Of

ABSTRACTUltra-shallow p+ junctions are required for next generation electronics. We present a technique for the formation of ultra-shallow p+ junctions that increases the thermal stability of the junctions formed by ion implantation. By using a 10 nm Si1−xGex barrier layer, the diffusion of B is inhibited during high temperature processes. Alloys having a composition from x = 0 to 0.4 were investigated and it is shown that the most effective barrier had the maximum Ge fraction. The junction depth decreased to 36.7 nm for a 5×1015/cm2 1kV BF3 plasma implant spike annealed at 1050°C, compared to a junction depth of 48 nm for a Si control sample having the identical implant and anneal. It is hypothesized that the inhibition of B diffusion in the alloy layer is caused by a reduction of the Si self-interstitials in the alloy.

A Model to Explain the Variations of “End-of-Range” Defect Densities with Ion Implantation Parameters

1992 ◽  
Vol 279 ◽  
Author(s):  
L. Laanab ◽  
C. Bergaud ◽  
M. M. Faye ◽  
J. Faure ◽  
A. Martinez ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Computer Simulations ◽  
Point Defects ◽  
Numerical Optimization ◽  
Experimental Investigations ◽  
Shallow Junctions ◽  
Quantitative Explanation ◽  
Defect Densities

ABSTRACTComputer simulations in conjunction with TEM experiments have been used to test the different models usually adopted in the literature to explain the formation of “End Of Range”(EOR) defects which appear after annealing of preamorphized silicon layers. Only one survives careful experimental investigations involving Si+, Ge+, Sn+ amorphization at RT and LNT. The “excess-interstitial” model appears relevant at least for a semi-quantitative explanation of the source of point-defects which after recombination and agglomeration, lead to the formation of these defects. This model may be used for the numerical optimization of conditions for the production of high performances ullra-shallow junctions.

Scanned Electron Beam Annealing of Boron-Implanted Diodes

1980 ◽  
Vol 1 ◽  
Author(s):  
T. O. Yep ◽  
R. T. Fulks ◽  
R. A. Powell
Keyword(s):  
Electron Beam ◽  
Ion Implantation ◽  
Reverse Bias ◽  
Carrier Lifetime ◽  
Reverse Current ◽  
Electrical Activation ◽  
Electrical Characteristics ◽  
Low Resolution ◽  
Implantation Damage ◽  
Dopant Redistribution

ABSTRACTSuccessful annealing of p+ n arrays fabricated by ion-implantation of 11B (50 keV, 1 × 1014 cm-2) into Si (100 has been performed using a broadly rastered, low-resolution (0.25-inch diameter) electron beam. A complete 2" wafer could be uniformly annealed in ≃20 sec with high electrical activation (>75%) and small dopant redistribution (≃450 Å). Annealing resulted In p+n junctions characterized by low reverse current (≃4 nAcm-2 at 5V reverse bias) and higher carrier lifetime (80 μsec) over the entire 2" wafer. Based on the electrical characteristics of the diodes, we estimate that the electron beam anneal was able to remove ion implantation damage and leave an ordered substrate to a depth of 5.5 m below the layer junction.

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