As and B Ion Implantation Through Mo and into Mo-Silicide Layers for Shallow Junction Formation

1989 ◽  
Vol 157 ◽  
Author(s):  
R. Angelucci ◽  
M. Merli ◽  
S. Solmi ◽  
A. Armigliato ◽  
E. Gabilli ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Carrier Concentration ◽  
Rapid Thermal Annealing ◽  
Current Density ◽  
Reverse Current ◽  
Concentration Profiles ◽  
Leakage Currents ◽  
Junction Formation ◽  
Shallow Junctions ◽  
Silicon Interface

ABSTRACTGood quality p+/n and n+/p shallow junctions (< 0.15 um) with reverse current density of few nA/cm2 and low contact resistivity (∼ 5×10–7 Ω cm2) have been fabricated by using Mo suicide and Rapid Thermal Annealing (RTA). The processes of implantation through Mo films and into MoSi2 layers have been comparatively analysed on the basis of SIMS and carrier concentration profiles, TEM observations and DLTS measurements. In the case of n+/p diodes fabricated by ITM technology slightly worse leakage currents have been observed, in spite of the better planarity of the silicide-silicon interface exhibited by these structures.

Rapid Thermal Anneaung of Arsenic-Phosphorus(N+-N-) Double-Diffused Shallow Junctions

1985 ◽  
Vol 52 ◽  
Author(s):  
D. L. Kwong ◽  
N. S. Alvi ◽  
Y. H. Ku ◽  
A. W. Cheung
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Experimental Results ◽  
Silicon Substrates ◽  
Electrical Characteristics ◽  
Shallow Junctions

ABSTRACTDouble-diffused shallow junctions have been formed by ion implantation of both phosphorus and arsenic ions into silicon substrates and rapid thermal annealing. Experimental results on defect removal, impurity activation and redistribution, effects of Si preamorphization, and electrical characteristics of Ti-silicided junctions are presented.

Formation of Cosi2-Shallow Junctions By Ion Beam Mixing and Rapid Thermal Annealing

1990 ◽  
Vol 181 ◽  
Author(s):  
L. Niewöhner ◽  
D. Depta
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Ion Beam ◽  
Dopant Distribution ◽  
Junction Depth ◽  
Ion Beam Mixing ◽  
Sem And Tem ◽  
Shallow Junctions

ABSTRACTFormation of CoSi2 using the technique of ion implantation through metal (ITM) and subsequent appropriate rapid thermal annealing is described. Silicide morphology is investigated by SEM and TEM. SIMS and RBS are used to determine dopant distribution and junction depth. Self-aligned CoSi2/n+p diodes produced in this technique are presented.

A Study of Damage in Silicon Created By and P+ Implantation

1988 ◽  
Vol 100 ◽  
Author(s):  
Fang Ziwei ◽  
Lin Chenglu ◽  
Tsou Shihchang
Keyword(s):  
Carrier Concentration ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Incident Energy ◽  
Room Temperature ◽  
Concentration Profiles ◽  
Molecular Fragments ◽  
Multiple Collision ◽  
Annealing Behavior ◽  
Intermediate Dose

ABSTRACTThe damage and annealing behavior of <100> Si implanted at room temperature by and P+ at different energies (5-600KeV) and intermediate dose (∼1014/cm2) has been investigated. Experimental results show that the damage created by implantation is always greater than that of P+ implantation. The ratio of total displaced atoms of the target cuased by molecular and atomic implantation, ND(mol)d/ND(atom) reached a maximal value at 100KeV () and 50KeV (P+) after rapid thermal annealing, the carrier concentration profiles measured by spreading resistance measurements are also different for the and P+ implanted samples. We attribute essentially this phenomenon to the displacement spike, but the multiple collision effect and the interaction between two molecular fragments should be considered while the incident energy is high.

Room Temperature Annealing Effects on Leakage Current of Ion Implanted p+n 4H-SiC Diodes

2008 ◽  
Vol 600-603 ◽  
pp. 1027-1030 ◽  
Author(s):  
Francesco Moscatelli ◽  
Fabio Bergamini ◽  
Antonella Poggi ◽  
Mara Passini ◽  
Fabrizio Tamarri ◽  
...  
Keyword(s):  
Leakage Current ◽  
Current Density ◽  
Room Temperature ◽  
Current Trend ◽  
Reverse Current ◽  
Metal Contacts ◽  
Leakage Currents ◽  
Forward Current ◽  
Annealing Effects ◽  
Order Of Magnitude

The current-voltage characteristics of Al+ implanted 4H-SiC p+n junctions show an important reduction of leakage currents with diode aging at room temperature. The case of a family of diodes that immediately after manufacture had forward current density increasing from 10-9 to 10-6 A/cm2 when biased from 0 and 2 V, and had a reverse leakage current density of @ 5×10-7 A/cm2 when biased at 100 V, is here presented and discussed. During diode manufacturing a post implantation annealing at 1600 °C for 30 min was followed by a 1000 °C 1 min treatment for metal contacts alloying. After 700 days of storage at room temperature, the diode reverse current density reached an asymptotical value of @ 4×10-11 A/cm2 that is four order of magnitude lower than the initial one. A 430 °C annealing that was made after 366 days is responsible of a decrease of one of these four orders of magnitude, but it does not interrupt the decreasing trend versus increasing time. This same annealing has been effective also for minimizing forward current for bias < 2 V, and sticking the diode turn-on voltage on 1.4 V and the current trend on an ideality factor of 2. These results show that in Al+ implanted 4H-SiC p+n junction there are defects that have an annihilation dynamic at very low temperatures, i.e. room temperature and 430 °C.

X-Ray Induced Depth Profiling of Ion Implantations into Various Semiconductor Materials

2012 ◽  
Vol 195 ◽  
pp. 274-276 ◽  
Author(s):  
Philipp Hönicke ◽  
Matthias Müller ◽  
Burkhard Beckhoff
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Measurement Techniques ◽  
Depth Profiling ◽  
Low Energy ◽  
Semiconductor Materials ◽  
Leakage Currents ◽  
X Ray ◽  
20 Nm

The continuing shrinking of the component dimensions in ULSI technology requires junction depths in the 20-nm regime and below to avoid leakage currents. These ultra shallow dopant distributions can be formed by ultra-low energy (ULE) ion implantation. However, accurate measurement techniques for ultra-shallow dopant profiles are required in order to characterize ULE implantation and the necessary rapid thermal annealing (RTA) processes.

Shallow Junctions for Sub-100 Nm Cmos Technology

2001 ◽  
Vol 669 ◽  
Author(s):  
Veerle Meyssen ◽  
Peter Stolk ◽  
Jeroen van Zijl ◽  
Jurgen van Berkum ◽  
Willem van de Wijgert ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Cmos Technology ◽  
Low Energy ◽  
Annealing Conditions ◽  
Delta Doping ◽  
Shallow Junctions ◽  
P Type ◽  
Spike Annealing

ABSTRACTThis paper studies the use of ion implantation and rapid thermal annealing for the fabrication of shallow junctions in sub-100 nm CMOS technology. Spike annealing recipes were optimized on the basis of delta-doping diffusion experiments and shallow junction characteristics. In addition, using GeF2 pre-amorphization implants in combination with low-energy BF2 and spike annealing, p-type junctions depths of 30 nm were obtained with sheet resistances as low as 390 Ω/sq. The combined finetuning of implantation and annealing conditions is expected to enable junction scaling into the 70-nm CMOS technology node.

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