Optimized Built-In Self-Test Technique for CAEN-Based Nanofabric Systems

Nanoelectronic Device Applications Handbook ◽

10.1201/b15035-45 ◽

2017 ◽

pp. 569-590

Author(s):

Maciej Zawodniok ◽

Sambhav Kundaikar

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters

2014 IEEE 32nd VLSI Test Symposium (VTS) ◽

10.1109/vts.2014.6818750 ◽

2014 ◽

Cited By ~ 3

Author(s):

Tao Liu ◽

Chao Fu ◽

Sule Ozev ◽

Bertan Bakkaloglu

Keyword(s):

Test Technique ◽

Current Sensing ◽

Self Test ◽

Built In Self Test

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A zero aliasing built-in self test technique for delay fault testing

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) ◽

10.1109/dftvs.1999.802874 ◽

2003 ◽

Cited By ~ 3

Author(s):

Y. Tsiatouhas ◽

T. Haniotakis

Keyword(s):

Fault Testing ◽

Test Technique ◽

Delay Fault ◽

Delay Fault Testing ◽

Self Test ◽

Built In Self Test

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An implementation and analysis of a concurrent built-in self-test technique

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers ◽

10.1109/ftcs.1988.5315 ◽

2003 ◽

Cited By ~ 26

Author(s):

R. Sharma ◽

K.K. Saluja

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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A built-in self-test technique for transmitter-only systems

2018 IEEE 36th VLSI Test Symposium (VTS) ◽

10.1109/vts.2018.8368636 ◽

2018 ◽

Author(s):

Maryam Shafiee ◽

Jennifer N. Kitchen ◽

Sule Ozev

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories

17th International Conference on VLSI Design. Proceedings. ◽

10.1109/icvd.2004.1261019 ◽

2004 ◽

Cited By ~ 4

Author(s):

R.S. Sable ◽

R.P. Saraf ◽

R.A. Parekhji ◽

A.N. Chandorkar

Keyword(s):

Selective Detection ◽

Test Technique ◽

Pattern Sensitive Faults ◽

Self Test ◽

Built In Self Test

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