New built-in self-test technique based on addition/subtraction of selected node voltages

Proceedings of the Ninth Asian Test Symposium ◽

10.1109/ats.2000.893600 ◽

2002 ◽

Cited By ~ 2

Author(s):

K.Y. Ko ◽

M.W.T. Wong

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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A built-in self-test technique for load inductance and lossless current sensing of DC-DC converters

2014 IEEE 32nd VLSI Test Symposium (VTS) ◽

10.1109/vts.2014.6818750 ◽

2014 ◽

Cited By ~ 3

Author(s):

Tao Liu ◽

Chao Fu ◽

Sule Ozev ◽

Bertan Bakkaloglu

Keyword(s):

Test Technique ◽

Current Sensing ◽

Self Test ◽

Built In Self Test

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A zero aliasing built-in self test technique for delay fault testing

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) ◽

10.1109/dftvs.1999.802874 ◽

2003 ◽

Cited By ~ 3

Author(s):

Y. Tsiatouhas ◽

T. Haniotakis

Keyword(s):

Fault Testing ◽

Test Technique ◽

Delay Fault ◽

Delay Fault Testing ◽

Self Test ◽

Built In Self Test

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An implementation and analysis of a concurrent built-in self-test technique

[1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers ◽

10.1109/ftcs.1988.5315 ◽

2003 ◽

Cited By ~ 26

Author(s):

R. Sharma ◽

K.K. Saluja

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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A built-in self-test technique for transmitter-only systems

2018 IEEE 36th VLSI Test Symposium (VTS) ◽

10.1109/vts.2018.8368636 ◽

2018 ◽

Author(s):

Maryam Shafiee ◽

Jennifer N. Kitchen ◽

Sule Ozev

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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Built-in self-test technique for selective detection of neighbourhood pattern sensitive faults in memories

17th International Conference on VLSI Design. Proceedings. ◽

10.1109/icvd.2004.1261019 ◽

2004 ◽

Cited By ~ 4

Author(s):

R.S. Sable ◽

R.P. Saraf ◽

R.A. Parekhji ◽

A.N. Chandorkar

Keyword(s):

Selective Detection ◽

Test Technique ◽

Pattern Sensitive Faults ◽

Self Test ◽

Built In Self Test

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Optimized built-in self-test technique for CAEN-based nanofabric systems

2011 11th IEEE International Conference on Nanotechnology ◽

10.1109/nano.2011.6144624 ◽

2011 ◽

Author(s):

Sambhav Kundaikar ◽

Maciej Zawodniok

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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An efficient comparative concurrent Built-In Self-Test technique

Proceedings of the Fourth Asian Test Symposium ◽

10.1109/ats.1995.485353 ◽

2002 ◽

Cited By ~ 4

Author(s):

I. Voyiatzis ◽

D. Nikolos ◽

A. Paschalis ◽

C. Halatsis ◽

T. Haniotakis

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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Optimized Built-In Self-Test Technique for CAEN-Based Nanofabric Systems

Nanoelectronic Device Applications Handbook ◽

10.1201/b15035-45 ◽

2017 ◽

pp. 569-590

Author(s):

Maciej Zawodniok ◽

Sambhav Kundaikar

Keyword(s):

Test Technique ◽

Self Test ◽

Built In Self Test

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A unified approach for a time-domain built-in self-test technique and fault detection

Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222) ◽

10.1109/glsv.1998.665234 ◽

2002 ◽

Cited By ~ 1

Author(s):

B. Provost ◽

A.M. Brosa ◽

E. Sanchez-Sinencio

Keyword(s):

Fault Detection ◽

Time Domain ◽

Unified Approach ◽

Test Technique ◽

Self Test ◽

Built In Self Test

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A Dual-Mode Built-in Self-Test Technique for Capacitive MEMS Devices

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2005.855094 ◽

2005 ◽

Vol 54 (5) ◽

pp. 1739-1750 ◽

Cited By ~ 32

Author(s):

X. Xiong ◽

Y.-L. Wu ◽

W.-B. Jone

Keyword(s):

Mems Devices ◽

Dual Mode ◽

Test Technique ◽

Self Test ◽

Built In Self Test ◽

Capacitive Mems

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