scholarly journals Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime UsingYandZFunctions

2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
A. Karsenty ◽  
A. Chelly
Keyword(s):  
Comparative Analysis ◽  
Low Temperature ◽  
Room Temperature ◽  
Series Resistance ◽  
Function Analysis ◽  
Saturation Regime ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Recessed Channel ◽  
First Time

The saturation regime of two types of fully depleted (FD) SOI MOSFET devices was studied. Ultrathin body (UTB) and gate recessed channel (GRC) devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the sameW/Lratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics (IDS-VDSandIDS-VGS) of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using aY-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of theY-function analysis and show that a new function calledZcan be used to extract the series resistance in the saturation regime.

scholarly journals Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

2015 ◽  
Vol 2015 ◽  
pp. 1-5
Author(s):  
Avi Karsenty ◽  
Avraham Chelly
Keyword(s):  
Low Temperature ◽  
Potential Barrier ◽  
Room Temperature ◽  
Short Channel ◽  
Anomalous Effect ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Thickness ◽  
Recessed Channel ◽  
Long Channel

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

Anomalous Kink Effect in Low-Dimensional Gate-Recessed Fully Depleted SOI MOSFET at Low Temperature

NANO ◽  
2015 ◽  
Vol 10 (07) ◽  
pp. 1550093 ◽  
Author(s):  
Avi Karsenty ◽  
Avraham Chelly
Keyword(s):  
Low Temperature ◽  
Room Temperature ◽  
Fully Depleted ◽  
Kink Effect ◽  
Channel Thickness ◽  
Extension Zone ◽  
Nanoscale Mosfets ◽  
Output Characteristics ◽  
Recessed Channel ◽  
Low Dimensional

Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (t SI ) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I–V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.

scholarly journals Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
A. Karsenty ◽  
A. Chelly
Keyword(s):  
Opposite Effect ◽  
Series Resistance ◽  
Function Analysis ◽  
Effective Field ◽  
Low Field ◽  
Channel Thickness ◽  
Great Relevance ◽  
Recessed Channel ◽  
Very High

The respective transfer characteristics of the ultrathin body (UTB) and gate recessed channel (GRC) device, sharing sameW/Lratio but having a channel thickness of 46 nm, and 2.2 nm respectively, were measured at 300 K and at 77 K. By decreasing the temperature we found that the electrical behaviors of these devices were radically opposite: if for UTB device, the conductivity was increased, the opposite effect was observed for GRC. The low field electron mobility and series resistanceRSDvalues were extracted using a method based onY-function for both the temperatures. IfRSDlow values were found for UTB, very high values (>1 MΩ) were extracted for GRC. Surprisingly, for the last device, the effective field mobility is found very low (<1 cm2/Vs) and is decreasing by lowering the temperature. After having discussed the limits of this analysis.This case study illustrates the advantage of theY-analysis in discriminating a parameter of great relevance for nanoscale devices and gives a coherent interpretation of an anomalous electrical behavior.

Low-temperature Raman and Fourier transform infrared spectra of dodecacarbonyldirhenium(0), Re2(CO)10

1985 ◽  
Vol 63 (7) ◽  
pp. 1510-1517 ◽  
Author(s):  
Pierre D. Harvey ◽  
Ian S. Butler
Keyword(s):  
Fourier Transform ◽  
Low Temperature ◽  
Room Temperature ◽  
Metal Carbonyl ◽  
Carbonyl Complex ◽  
X Ray ◽  
Temperature Spectra ◽  
Ft Ir ◽  
Ir Study ◽  
First Time

The Raman spectrum of microcrystalline dodecacarbonyldirhenium(0), Re2(CO)10, has been reinvestigated at 67 K using one of the latest fully-computerized spectrometers available. Previously unobserved peaks have been detected mainly in the 13CO-satellite (2150–1900 cm−1), and overtone and combination regions (1300–700 and 4300–3800 cm−1). This is the first time that Raman-active first CO overtones and combinations of a metal carbonyl complex have been reported. They were earlier thought to be too weak to be detected. Assignments are proposed for the majority of these new peaks together with those from a similar low-temperature (~70 K) FT-ir study. In general, the D4d selection rules are obeyed, but the activity of some forbidden bands reveals that the molecule is slightly distorted in the solid state in agreement with its X-ray structure. The similarity of the low-temperature spectra to those obtained at room temperature indicates that no phase change occurs throughout the temperature range investigated.

scholarly journals Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

2013 ◽  
Vol 2013 ◽  
pp. 1-10 ◽  
Author(s):  
A. Karsenty ◽  
A. Chelly
Keyword(s):  
Room Temperature ◽  
Series Resistance ◽  
Electrical Characteristics ◽  
Saturation Current ◽  
Mobility Degradation ◽  
Current Voltage ◽  
Voltage Dependent ◽  
Channel Thickness ◽  
Current Voltage Characteristics ◽  
First Time

Ultrathin body (UTB) and nanoscale body (NSB) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

1997 ◽  
Vol 44 (9) ◽  
pp. 1467-1472 ◽  
Author(s):  
T. Ushiki ◽  
Mo-Chiun Yu ◽  
Y. Hirano ◽  
H. Shimada ◽  
M. Morita ◽  
...  
Keyword(s):  
Low Temperature ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Low Temperature Processing

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

1994 ◽  
Vol 15 (1) ◽  
pp. 22-24 ◽  
Author(s):  
M. Chan ◽  
F. Assaderaghi ◽  
S.A. Parke ◽  
C. Hu ◽  
P.K. Ko
Keyword(s):  
Series Resistance ◽  
Channel Structure ◽  
Soi Mosfet ◽  
Recessed Channel ◽  
Ultrathin Soi

Survival of mouse blastocysts after low-temperature preservation under high pressure

2004 ◽  
Vol 52 (4) ◽  
pp. 479-487 ◽  
Author(s):  
Cs. Pribenszky ◽  
M. Molnár ◽  
S. Cseh ◽  
L. Solti
Keyword(s):  
Phase Transition ◽  
Hydrostatic Pressure ◽  
Low Temperature ◽  
High Hydrostatic Pressure ◽  
Room Temperature ◽  
Freezing Point ◽  
Significant Loss ◽  
Embryo Cryopreservation ◽  
Subzero Temperatures ◽  
Survival Capacity

Cryoinjuries are almost inevitable during the freezing of embryos. The present study examines the possibility of using high hydrostatic pressure to reduce substantially the freezing point of the embryo-holding solution, in order to preserve embryos at subzero temperatures, thus avoiding all the disadvantages of freezing. The pressure of 210 MPa lowers the phase transition temperature of water to -21°C. According to the results of this study, embryos can survive in high hydrostatic pressure environment at room temperature; the time embryos spend under pressure without significant loss in their survival could be lengthened by gradual decompression. Pressurisation at 0°C significantly reduced the survival capacity of the embryos; gradual decompression had no beneficial effect on survival at that stage. Based on the findings, the use of the phenomena is not applicable in this form, since pressure and low temperature together proved to be lethal to the embryos in these experiments. The application of hydrostatic pressure in embryo cryopreservation requires more detailed research, although the experience gained in this study can be applied usefully in different circumstances.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

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