scholarly journals Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

2015 ◽  
Vol 2015 ◽  
pp. 1-5
Author(s):  
Avi Karsenty ◽  
Avraham Chelly
Keyword(s):  
Low Temperature ◽  
Potential Barrier ◽  
Room Temperature ◽  
Short Channel ◽  
Anomalous Effect ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Thickness ◽  
Recessed Channel ◽  
Long Channel

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) forI-Vcharacterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

scholarly journals Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime UsingYandZFunctions

2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
A. Karsenty ◽  
A. Chelly
Keyword(s):  
Comparative Analysis ◽  
Low Temperature ◽  
Room Temperature ◽  
Series Resistance ◽  
Function Analysis ◽  
Saturation Regime ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Recessed Channel ◽  
First Time

The saturation regime of two types of fully depleted (FD) SOI MOSFET devices was studied. Ultrathin body (UTB) and gate recessed channel (GRC) devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the sameW/Lratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics (IDS-VDSandIDS-VGS) of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using aY-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of theY-function analysis and show that a new function calledZcan be used to extract the series resistance in the saturation regime.

Anomalous Kink Effect in Low-Dimensional Gate-Recessed Fully Depleted SOI MOSFET at Low Temperature

NANO ◽  
2015 ◽  
Vol 10 (07) ◽  
pp. 1550093 ◽  
Author(s):  
Avi Karsenty ◽  
Avraham Chelly
Keyword(s):  
Low Temperature ◽  
Room Temperature ◽  
Fully Depleted ◽  
Kink Effect ◽  
Channel Thickness ◽  
Extension Zone ◽  
Nanoscale Mosfets ◽  
Output Characteristics ◽  
Recessed Channel ◽  
Low Dimensional

Nanoscale MOSFETs Gate-Recessed Channel (GRC) device with a silicon channel thickness (t SI ) as low as 2.2 nm was first tested at room temperature for functionality check, and then tested at low temperature (77 K) for I–V characterizations. In spite of its FD-SOI nanoscale thickness, the GRC device has surprisingly exhibited a Kink Effect in the output characteristics at 77 K. The anomalous Kink Effect can be explained by the increase of the lateral electric field in the drain junction with the channel extension zone when lowering the temperature.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Anjali Priya ◽  
Nilesh Anand Srivastava ◽  
Ram Awadh Mishra
Keyword(s):  
Threshold Voltage ◽  
Propagation Delay ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Gate Length ◽  
Metal Gate ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Silvaco Atlas

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Modeling of Sub Threshold Current and Sub Threshold Swing of Short-Channel Fully-Depleted SOI MOSFET with Back-Gate Control

2017 ◽  
Vol 9 (01) ◽  
pp. 67-72
Author(s):  
Sarvesh Dubey ◽  
Rahul Mishra
Keyword(s):  
Analytical Modeling ◽  
Threshold Current ◽  
Short Channel Effects ◽  
Short Channel ◽  
Simulation Data ◽  
Back Gate ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
Gate Control

The present paper deals with the analytical modeling of subthreshold characteristics of short-channel fully-depleted recessed-source/drain SOI MOSFET with back-gate control. The variations in the subthreshold current and subthreshold swing have been analyzed against the back-gate bias voltage, buried-oxide (BOX) thickness and recessed source/drain thickness to assess the severity of short-channel effects in the device. The model results are validated by simulation data obtained from two-dimensional device simulator ATLAS from Silvaco.

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

2017 ◽  
Vol 27 (04) ◽  
pp. 1850063 ◽  
Author(s):  
Rajneesh Sharma ◽  
Rituraj S. Rathore ◽  
Ashwani K. Rana
Keyword(s):  
Dielectric Materials ◽  
Channel Length ◽  
Silicon On Insulator ◽  
Device Performance ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects ◽  
The Impact ◽  
Gate Underlap

The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current ([Formula: see text]). However, the gate underlap also results in reduced ON current ([Formula: see text]) due to increased effective channel length. The use of high-[Formula: see text] material as a spacer region helps to achieve the higher [Formula: see text] but at the cost of increased effective gate capacitance ([Formula: see text]) which degrades the device performance. Thus, the impact of high-[Formula: see text] spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text]/[Formula: see text] ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the [Formula: see text]/[Formula: see text] ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10[Formula: see text]nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in [Formula: see text] especially below 20[Formula: see text]nm gate length.

Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

2006 ◽  
Vol 53 (9) ◽  
pp. 2017-2024 ◽  
Author(s):  
N. Sadachika ◽  
D. Kitamaru ◽  
Y. Uetsuji ◽  
D. Navarro ◽  
M.M. Yusoff ◽  
...  
Keyword(s):  
Surface Potential ◽  
Compact Model ◽  
Short Channel Effects ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects

Reliable tantalum-gate fully-depleted-SOI MOSFET technology featuring low-temperature processing

1997 ◽  
Vol 44 (9) ◽  
pp. 1467-1472 ◽  
Author(s):  
T. Ushiki ◽  
Mo-Chiun Yu ◽  
Y. Hirano ◽  
H. Shimada ◽  
M. Morita ◽  
...  
Keyword(s):  
Low Temperature ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Low Temperature Processing
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