Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

1994 ◽  
Vol 15 (1) ◽  
pp. 22-24 ◽  
Author(s):  
M. Chan ◽  
F. Assaderaghi ◽  
S.A. Parke ◽  
C. Hu ◽  
P.K. Ko
Keyword(s):  
Series Resistance ◽  
Channel Structure ◽  
Soi Mosfet ◽  
Recessed Channel ◽  
Ultrathin Soi

scholarly journals Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime UsingYandZFunctions

2014 ◽  
Vol 2014 ◽  
pp. 1-8
Author(s):  
A. Karsenty ◽  
A. Chelly
Keyword(s):  
Comparative Analysis ◽  
Low Temperature ◽  
Room Temperature ◽  
Series Resistance ◽  
Function Analysis ◽  
Saturation Regime ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Recessed Channel ◽  
First Time

The saturation regime of two types of fully depleted (FD) SOI MOSFET devices was studied. Ultrathin body (UTB) and gate recessed channel (GRC) devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the sameW/Lratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics (IDS-VDSandIDS-VGS) of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using aY-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of theY-function analysis and show that a new function calledZcan be used to extract the series resistance in the saturation regime.

An Analytical Modeling and Performance Analysis of Graded Work Function Gate Recessed Channel SOI-MOSFET

2019 ◽  
Vol 9 (4) ◽  
pp. 504-511
Author(s):  
Sikha Mishra ◽  
Urmila Bhanja ◽  
Guru Prasad Mishra
Keyword(s):  
Analytical Model ◽  
Surface Potential ◽  
Threshold Voltage ◽  
Silicon On Insulator ◽  
Junction Depth ◽  
Short Channel ◽  
Soi Mosfet ◽  
Minimum Surface ◽  
Recessed Channel ◽  
The Impact

Introduction: A new analytical model is designed for Workfunction Modulated Rectangular Recessed Channel-Silicon On Insulator (WMRRC-SOI) MOSFET that considers the concept of groove gate and implements an idea of workfunction engineering. Methods: The impact of Negative Junction Depth (NJD) and oxide thickness (tox) are analyzed on device performances such as Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL) and threshold voltage. Results: The results of the proposed work are evaluated with the Rectangular Recessed Channel-Silicon On Insulator (RRC-SOI) MOSFET keeping the metal workfunction constant throughout the gate region. Furthermore, an analytical model is developed using 2D Poisson’s equation and threshold voltage is estimated in terms of minimum surface potential. Conclusion: In this work, the impact of Negative Junction Depth (NJD) on minimum surface potential and the drain current are also evaluated. It is observed from the analysis that the analog switching performance of WMRRC-SOI MOSFET surpasses RRC-SOI MOSFET in terms of better driving capability, high Ion/Ioff ratio, minimized Short Channel Effects (SCEs) and hot carrier immunity. Results are simulated using 2D Sentaurus TCAD simulator for validation of the proposed structure.

scholarly journals Usage and Limitation of Standard Mobility Models for TCAD Simulation of Nanoscaled FD-SOI MOSFETs

2015 ◽  
Vol 2015 ◽  
pp. 1-9 ◽  
Author(s):  
A. Ciprut ◽  
A. Chelly ◽  
A. Karsenty
Keyword(s):  
Gate Voltage ◽  
Series Resistance ◽  
Mobility Models ◽  
Soi Mosfet ◽  
Semiempirical Approach ◽  
Voltage Dependent ◽  
Channel Thickness ◽  
Dependent Series ◽  
Tcad Simulation ◽  
Or Gate

TCAD tools have been largely improved in the last decades in order to support both process and device complementary simulations which are usually based on continuously developed models following the technology progress. In this paper, we compare between experimental and TCAD simulated results of two kinds of nanoscale devices: ultrathin body (UTB) and nanoscale Body (NSB) SOI-MOSFET devices, sharing the sameW/Lratio but having a channel thickness ratio of 10 : 1 (46 nm and 4.6 nm, resp.). The experimental transferI-Vcharacteristics were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a large gate voltage dependent series resistance (RSD). TCAD tools do not usually considerRSDto be either channel thickness or gate voltage dependent. After observing a clear discrepancy between the mobility values extracted from our measurements and those modeled by the available TCAD models, we propose a new semiempirical approach to model the transfer characteristics.

FN-tunneling-current Modeling in a Recessed-channel Structure

2017 ◽  
Vol 17 (5) ◽  
pp. 709-716
Author(s):  
Young Kwon Kim ◽  
Taesik Park ◽  
Jin Sung Lee ◽  
Geon Kim ◽  
Hui Jung Kim ◽  
...  
Keyword(s):  
Tunneling Current ◽  
Channel Structure ◽  
Recessed Channel

Suppressed threshold voltage roll-off characteristic of 40 nm gate length ultrathin SOI MOSFET

1998 ◽  
Vol 34 (21) ◽  
pp. 2069 ◽  
Author(s):  
K. Ishii ◽  
E. Suzuki ◽  
S. Kanemaru ◽  
T. Maeda ◽  
K. Nagai ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Length ◽  
Soi Mosfet ◽  
Ultrathin Soi
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