scholarly journals Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test

VLSI Design ◽  
2008 ◽  
Vol 2008 ◽  
pp. 1-9 ◽  
Author(s):  
Yves Joannon ◽  
Vincent Beroulle ◽  
Chantal Robach ◽  
Smail Tedjini ◽  
Jean-Louis Carbonero
Keyword(s):  
Fault Simulation ◽  
Fault Model ◽  
Test Set ◽  
Abstraction Level ◽  
Validation Test ◽  
Systems On Chip ◽  
Manufacturing Test ◽  
On Chip ◽  
High Level ◽  
Abstraction Levels

With the growing complexity of wireless systems on chip integrating hundreds-of-millions of transistors, electronic design methods need to be upgraded to reduce time-to-market. In this paper, the test benches defined for design validation or characterization of AMS & RF SoCs are optimized and reused for production testing. Although the original validation test set allows the verification of both design functionalities and performances, this test set is not well adapted to manufacturing test due to its high execution time and high test equipment costs requirement. The optimization of this validation test set is based on the evaluation of each test vector. This evaluation relies on high-level fault modeling and fault simulation. Hence, a fault model based on the variations of the parameters of high abstraction level descriptions and its related qualification metric are presented. The choice of functional or behavioral abstraction levels is discussed by comparing their impact on structural fault coverage. Experiments are performed on the receiver part of a WCDMA transceiver. Results show that for this SoC, using behavioral abstraction level is justified for the generation of manufacturing test benches.

From MARTE to Reconfigurable NoCs

2010 ◽  
pp. 135-157
Author(s):  
Imran Rafiq Quadri ◽  
Majdi Elhaji ◽  
Samy Meftali ◽  
Jean-Luc Dekeyser
Keyword(s):  
System Modeling ◽  
Unified Modeling Language ◽  
Modeling And Analysis ◽  
Unified Modeling ◽  
Model Driven ◽  
Abstraction Level ◽  
Management Group ◽  
High Level Modeling ◽  
High Level ◽  
Abstraction Levels

Due to the continuous exponential rise in SoC’s design complexity, there is a critical need to find new seamless methodologies and tools to handle the SoC co-design aspects. We address this issue and propose a novel SoC co-design methodology based on Model Driven Engineering and the MARTE (Modeling and Analysis of Real-Time and Embedded Systems) standard proposed by Object Management Group, to raise the design abstraction levels. Extensions of this standard have enabled us to move from high level specifications to execution platforms such as reconfigurable FPGAs. In this chapter, we present a high level modeling approach that targets modern Network on Chips systems. The overall objective: to perform system modeling at a high abstraction level expressed in Unified Modeling Language (UML); and afterwards, transform these high level models into detailed enriched lower level models in order to automatically generate the necessary code for final FPGA synthesis.

scholarly journals A Signature-Based Power Model for MPSoC on FPGA

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Roberta Piscitelli ◽  
Andy D. Pimentel
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Power Estimation ◽  
System Level ◽  
Estimation Methods ◽  
Instruction Set ◽  
Systems On Chip ◽  
Event Signatures ◽  
On Chip ◽  
High Level

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

2012 ◽  
pp. 263-277
Author(s):  
Sanna Määttä ◽  
Leandro Möller ◽  
Leandro Soares Indrusiak ◽  
Luciano Ost ◽  
Manfred Glesner ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Space Exploration ◽  
Network On Chip ◽  
Multiprocessor Systems ◽  
Trade Off ◽  
Successive Refinement ◽  
Systems On Chip ◽  
On Chip ◽  
Abstraction Levels

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

scholarly journals High level modeling of Dynamic Reconfigurable FPGAs

2009 ◽  
Vol 2009 ◽  
pp. 1-15 ◽  
Author(s):  
Imran Rafiq Quadri ◽  
Samy Meftali ◽  
Jean-Luc Dekeyser
Keyword(s):  
Embedded Systems ◽  
System Modeling ◽  
Unified Modeling Language ◽  
Modeling And Analysis ◽  
Model Driven ◽  
Fine Grain ◽  
Industry Standard ◽  
On Chip ◽  
High Level ◽  
Abstraction Levels

As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformation of these models automatically generate the necessary code for FPGA synthesis.

Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model

2015 ◽  
Author(s):  
Elmira Karimi ◽  
Mohammad-Hashem Haghbayan ◽  
Amir-Mohammad Rahmani ◽  
Mahmoud Tabandeh ◽  
Pasi Liljeberg ◽  
...  
Keyword(s):  
Fault Model ◽  
Test Methodology ◽  
On Chip ◽  
High Level

scholarly journals An Approach for Power Estimation at Electronic System Level using Distributed Simulation

2016 ◽  
Vol 11 (3) ◽  
pp. 159-170
Author(s):  
Helder F. A. Oliveira ◽  
Alisson V. Brito ◽  
Joseana M. F. R. Araujo ◽  
Elmar U. K. Melcher
Keyword(s):  
Distributed Simulation ◽  
Power Estimation ◽  
Electronic System ◽  
System Level ◽  
Multiprocessor System ◽  
High Level Architecture ◽  
Electronic System Level ◽  
On Chip ◽  
High Level ◽  
Abstraction Levels

The present research aims to develop an approach using HLA (High Level Architecture), enabling the cre-ation of a distributed and heterogeneous environment, composed by different tools and models to obtain a better trade-off between accuracy and run time in power estimation. These models can be described in different languages and/or abstraction levels, as well as use different power estimation approaches. The use of HLA enables the synchronized and distributed simulation of the elements that compose the simulation environment. The approach must allow the collecting and grouping of power estimation data in a centralized manner. As a case study, an MPSoC (MultiProcessor System-on-Chip) ESL/TLM model, described in C++/SystemC, and an ESL model, created on Ptolemy framework, have been used. The experimental results show the flexibility of the approach, which promotes an integrated view of power estimation data.

scholarly journals Distributed Fault Simulation Algorithms on Parallel Virtual Machine

VLSI Design ◽  
2001 ◽  
Vol 12 (1) ◽  
pp. 81-99 ◽  
Author(s):  
C. P. Ravikumar ◽  
Vikas Jain ◽  
Anurag Dod
Keyword(s):  
Virtual Machine ◽  
Distributed Algorithms ◽  
Fault Simulation ◽  
Fault Model ◽  
Experimental Results ◽  
Sequential Algorithm ◽  
Set Partition ◽  
Compression Technique ◽  
Test Set ◽  
Parallel Virtual Machine

In this paper, we describe distributed algorithms for combinational fault simulation assuming the classical stuck-at fault model. Our algorithms have been implemented on a network of Sun workstations under the Parallel Virtual Machine (PVM) environment. Two techniques are used for subdividing work among processors – test set partition and fault set partition. The sequential algorithm for fault simulation, used on individual nodes of the network, is based on a novel path compression technique proposed in this paper. We describe experimental results on a number of ISCAS′85 benchmark circuits.

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