scholarly journals A Signature-Based Power Model for MPSoC on FPGA

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-13 ◽  
Author(s):  
Roberta Piscitelli ◽  
Andy D. Pimentel
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Power Estimation ◽  
System Level ◽  
Estimation Methods ◽  
Instruction Set ◽  
Systems On Chip ◽  
Event Signatures ◽  
On Chip ◽  
High Level

This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.

System-Level Design of NoC-Based Dependable Embedded Systems

2014 ◽  
pp. 478-512
Author(s):  
Mihkel Tagel ◽  
Peeter Ellervee ◽  
Gert Jervan
Keyword(s):  
Design Space Exploration ◽  
System Level ◽  
System Level Design ◽  
Levels Of Abstraction ◽  
Technology Scaling ◽  
Communication Problems ◽  
Systems On Chip ◽  
Level Design ◽  
On Chip ◽  
Manufacturing Yield

Technology scaling into subnanometer range will have impact on the manufacturing yield and quality. At the same time, complexity and communication requirements of systems-on-chip (SoC) are increasing, thus making a SoC designer goal to design a fault-free system a very difficult task. Network-on-chip (NoC) has been proposed as one of the alternatives to solve some of the on-chip communication problems and to address dependability at various levels of abstraction. This chapter concentrates on system-level design issues of NoC-based systems. It describes various methods proposed for NoC architecture analysis and optimization, and gives an overview of different system-level fault tolerance methods. Finally, the chapter presents a system-level design framework for performing design space exploration for dependable NoC-based systems.

A correlation-based design space exploration methodology for multi-processor systems-on-chip

2010 ◽  
Author(s):  
Giovanni Mariani ◽  
Aleksandar Brankovic ◽  
Gianluca Palermo ◽  
Jovana Jovic ◽  
Vittorio Zaccaria ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Systems On Chip ◽  
On Chip

scholarly journals A Design Space Exploration Framework for ANN-Based Fault Detection in Hardware Systems

2017 ◽  
Vol 2017 ◽  
pp. 1-12
Author(s):  
Andreas G. Savva ◽  
Theocharis Theocharides ◽  
Chrysostomos Nicopoulos
Keyword(s):  
Fault Detection ◽  
Design Space Exploration ◽  
Design Space ◽  
Generalization Capability ◽  
Networks On Chip ◽  
Traffic Models ◽  
Artificial Neural Network Ann ◽  
On Chip ◽  
High Level

This work presents a design exploration framework for developing a high level Artificial Neural Network (ANN) for fault detection in hardware systems. ANNs can be used for fault detection purposes since they have excellent characteristics such as generalization capability, robustness, and fault tolerance. Designing an ANN in order to be used for fault detection purposes includes different parameters. Through this work, those parameters are presented and analyzed based on simulations. Moreover, after the development of the ANN, in order to evaluate it, a case study scenario based on Networks on Chip is used for detection of interrouter link faults. Simulation results with various synthetic traffic models show that the proposed work can detect up to 96–99% of interrouter link faults with a delay less than 60 cycles. Added to this, the size of the ANN is kept relatively small and they can be implemented in hardware easily. Synthesis results indicate an estimated amount of 0.0523 mW power consumption per neuron for the implemented ANN when computing a complete cycle.

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