2015 10th International Design & Test Symposium (IDT)
Latest Publications

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Published By IEEE

9781467399944

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SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396748 ◽

2015 ◽

Cited By ~ 3

Author(s):

Abdallatif S. Abu-Issa ◽

Iyad K. Tumar ◽

Wasel T. Ghanem

Keyword(s):

Test Pattern ◽

Pattern Generator

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Technical program committee

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396719 ◽

2015 ◽

Keyword(s):

Program Committee ◽

Technical Program Committee ◽

Technical Program

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FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystem

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396750 ◽

2015 ◽

Author(s):

A. Bellemou ◽

M. Anane ◽

N. Benblidia ◽

M. Issad

Keyword(s):

Elliptic Curve ◽

Fpga Implementation ◽

Scalar Multiplication ◽

Elliptic Curve Cryptosystem

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Chairs' message

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396720 ◽

2015 ◽

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Keynote 1: "Merger mania"

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396721 ◽

2015 ◽

Author(s):

Hanna Windele

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NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulation

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396743 ◽

2015 ◽

Author(s):

Samir Ben Abid ◽

Nejib Mediouni ◽

Oussama Kallel ◽

Salem Hasnaoui

Keyword(s):

Performance Evaluation ◽

Discrete Event Simulation ◽

Discrete Event ◽

Matlab Simulink ◽

Event Simulation ◽

Switch Performance ◽

Architectural Exploration

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Guiding intelligent testbench automation using data mining and formal methods

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396737 ◽

2015 ◽

Author(s):

Eman El Mandouh ◽

Amr G. Wassal

Keyword(s):

Data Mining ◽

Formal Methods ◽

Using Data

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Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann"

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396722 ◽

2015 ◽

Author(s):

Said Hamdioui

Keyword(s):

Big Data ◽

Von Neumann ◽

Beyond Cmos

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Efficient data management on 3D stacked memory for big data applications

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396741 ◽

2015 ◽

Cited By ~ 2

Author(s):

Cheng Qian ◽

Libo Huang ◽

Peng Xie ◽

Nong Xiao ◽

Zhiying Wang

Keyword(s):

Big Data ◽

Data Management ◽

Big Data Applications ◽

Efficient Data ◽

Stacked Memory

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Chip-level programming of heterogeneous multiprocessors

2015 10th International Design & Test Symposium (IDT) ◽

10.1109/idt.2015.7396730 ◽

2015 ◽

Author(s):

Mwaffaq Otoom ◽

JoAnn M. Paul

Keyword(s):

Heterogeneous Multiprocessors

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2015 10th International Design & Test Symposium (IDT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST

Technical program committee

FPGA implementation of scalar multiplication over Fp for elliptic curve cryptosystem

Chairs' message

Keynote 1: "Merger mania"

NRTBox: A Matlab Simulink toolbox for NoC switch performance evaluation and early architectural exploration using discrete event simulation

Guiding intelligent testbench automation using data mining and formal methods

Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann"

Efficient data management on 3D stacked memory for big data applications

Chip-level programming of heterogeneous multiprocessors

2015 10th International Design & Test Symposium (IDT)
Latest Publications