Effect of Ultrathin Silicon Oxide Film for Enhanced Performance and Reliability of Metal-Induced Laterally Crystallized Thin-Film Transistors Using Silicon Nitride as a Gate Dielectric

2016 ◽  
Vol 5 (12) ◽  
pp. Q279-Q283 ◽  
Author(s):  
Hee Jae Chae ◽  
Hyung Yoon Kim ◽  
Sol Kyu Lee ◽  
Ki Hwan Seok ◽  
Yong Hee Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Oxide Film ◽  
Thin Film Transistors ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
Silicon Oxide Film

High-Quality Solution-Processed Silicon Oxide Gate Dielectric Applied on Indium Oxide Based Thin-Film Transistors

2015 ◽  
Vol 7 (25) ◽  
pp. 14011-14017 ◽  
Author(s):  
Felix Jaehnike ◽  
Duy Vu Pham ◽  
Ralf Anselmann ◽  
Claudia Bock ◽  
Ulrich Kunze
Keyword(s):  
Thin Film ◽  
Indium Oxide ◽  
Thin Film Transistors ◽  
Silicon Oxide ◽  
Gate Dielectric ◽  
High Quality ◽  
Solution Processed

Reliability of Silicon Nitride Gate Dielectric in Vertical Thin-Film Transistors

2007 ◽  
Vol 989 ◽  
Author(s):  
Maryam Moradi ◽  
D. Striakhilev ◽  
I. Chan ◽  
A. Nathan ◽  
N. I. Cho ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Electrical Breakdown ◽  
Thick Films ◽  
Experimental Result ◽  
Process Conditions ◽  
Vertical Sidewall

AbstractIn this work, we have conducted a systematic investigation of leakage current and electrical breakdown of plasma enhanced chemical vapor deposited (PECVD) silicon nitride, both for planar films and deposited films on the vertical sidewall for the application of the vertical thin film transistors. The thickness evolution of physical properties and electrical characteristics of silicon nitride films in the range of 50 to 300 nm are investigated. Electrical breakdown strength for 150-300nm thick films was approximately 7 MV/cm, whereas the value dropped to ~3MV/cm for 50nm thick films deposited under the same process conditions. It is shown that the early failure of the thin nitride is accompanied by the increase of the pinholes number. For the vertical thin film transistors, the experimental result shows the reliability and leakage current of the gate dielectric depends on the step coverage of the silicon nitride film on the vertical sidewall.

Impact of Silicon Nitride Gate Dielectric Composition on the Stability of Low Temperature Nanocrystalline Silicon Thin Film Transistors

2019 ◽  
Vol 35 (4) ◽  
pp. 73-79
Author(s):  
Mohammad Esmaeili-Rad ◽  
Gholamreza Chaji ◽  
Flora Li ◽  
Maryam Moradi ◽  
Andrei Sazonov ◽  
...  
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Nanocrystalline Silicon ◽  
Silicon Thin Film ◽  
The Stability

Performance of Polycrystalline Silicon Thin Film Transistors with Double Layer Gate Dielectric

1992 ◽  
Vol 284 ◽  
Author(s):  
Ji-Ho Kung ◽  
Miltiadis K. Hatalis ◽  
Jerzy Kanicki
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Silicon Dioxide ◽  
Double Layer ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Nitride Layer ◽  
Silicon Thin Film ◽  
Bias Stress ◽  
Effective Carrier

ABSTRACTThe electrical characteristics of n- and p-channel poly-Si thin film transistors having a double layer gate dielectric structure are reported. The gate dielectric consists of a silicon dioxide layer and a nitrogen-rich silicon nitride layer, both deposited by PECVD at low temperatures (≥400° C). When the silicon nitride was in contact with the poly-Si film, the effective carrier mobility (μeff), threshold voltage (Vth and subthreshold swing (St) for n-channel devices were 36 cm2/Vsec, -1.8 V and 1.65 V/decade, respectively, while for p-channel devices were 6 cm2/Vsec, -37 and 2.47 V/decade, respectively. These devices were not stable under negative gate bias stress, due to the injection of holes into the silicon nitride. When silicon dioxide was in contact with the poly-Si film, the μeff, Vth and St for n-channel devices were 26 cm2/Vsec, 3 V and 1.63 V/decade, respectively, while for p-channel devices were 10 cm2/Vsec, -22 V and 1.52 V/decade, respectively. These devices were stable under d.c. bias stress.

Spin-Dependent Transport in Si Thin-Film Transistors

1997 ◽  
Vol 467 ◽  
Author(s):  
G. Kawachi ◽  
C F. O. Graeff ◽  
M. S. Brandt ◽  
M. Stutzmann
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Thin Film Transistors ◽  
Carrier Transport ◽  
Gate Dielectric ◽  
Signal To Noise Ratio ◽  
Nitride Layer ◽  
Transport Processes ◽  
Spin Dependent Transport ◽  
Dependent Transport

ABSTRACTDefects and carrier transport processes in silicon based thin-film transistors (TFTs) are investigated by spin-dependent transport (SDT). The resonance signal arising from less than 106 defects in the hydrogenated amorphous silicon (a-Si:H) TFT is detected with a sufficient signal-to-noise ratio. The leakage current mechanism in a-Si:H under high source-drain fields is identified by SDT as electron hopping via defect states located at the interface between undoped a-Si:H and the passivation silicon nitride layer. At temperatures below 100K, spin-dependent hopping of electrons in conduction band tail states is observed. The change of the dominant transport path from extended states conduction to variable range hopping with decreasing temperature is confirmed. SDT measurements on polycrystalline silicon (poly-Si) TFTs having silicon nitride and silicon dioxide as the gate dielectric films reveal differences in the defect structure in these devices. The overall results demonstrate that SDT is a powerful method to probe paramagnetic defects and carrier transport in TFTs.

Effect of Gate Dielectric on Performance of Polysilicon thin Film Transistors

1990 ◽  
Vol 182 ◽  
Author(s):  
Miltiadis K. Hatalis ◽  
Ji-Ho Kung ◽  
Jerzy Kanicki ◽  
Arthur A. Bright
Keyword(s):  
Thin Film ◽  
Silicon Nitride ◽  
Silicon Dioxide ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Gate Bias ◽  
Effective Electron ◽  
Bias Stress ◽  
Gate Bias Stress

AbstractThe effect of gate dielectric on the electrical characteristics of n-channel polysilicon thin film transistors was investigated. The following insulators were studied: silicon dioxide grown by wet oxidation, silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD) and nitrogen-rich silicon nitride deposited by PECVD. It was observed that the effective electron mobility in TFTs having a deposited dielectric, either silicon nitride or silicon dioxide was higher than that measured in devices with grown silicon dioxide. The TFT leakage current was found to be lowest in devices with PECVD silicon nitride. Devices with deposited dielectrics did not degrade after a positive gate bias stress. However, reduction of the threshold voltage was observed in devices with PECVD silicon nitride, when they were subjected to a negative gate bias stress.

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