Performance of Polycrystalline Silicon Thin Film Transistors with Double Layer Gate Dielectric

ABSTRACTThe electrical characteristics of n- and p-channel poly-Si thin film transistors having a double layer gate dielectric structure are reported. The gate dielectric consists of a silicon dioxide layer and a nitrogen-rich silicon nitride layer, both deposited by PECVD at low temperatures (≥400° C). When the silicon nitride was in contact with the poly-Si film, the effective carrier mobility (μeff), threshold voltage (Vth and subthreshold swing (St) for n-channel devices were 36 cm2/Vsec, -1.8 V and 1.65 V/decade, respectively, while for p-channel devices were 6 cm2/Vsec, -37 and 2.47 V/decade, respectively. These devices were not stable under negative gate bias stress, due to the injection of holes into the silicon nitride. When silicon dioxide was in contact with the poly-Si film, the μeff, Vth and St for n-channel devices were 26 cm2/Vsec, 3 V and 1.63 V/decade, respectively, while for p-channel devices were 10 cm2/Vsec, -22 V and 1.52 V/decade, respectively. These devices were stable under d.c. bias stress.