TiN Metal Hardmask Etch Residues Removal for Cu Dual Damascene Devices with TiN Mask Corner Rounding Scheme

2019 ◽  
Vol 44 (1) ◽  
pp. 377-381 ◽  
Author(s):  
Hua Cui
Keyword(s):  
Dual Damascene ◽  
Tin Metal

Effective Defect Control in TiN Metal Hard Mask Cu/Low-k Dual Damascene Process

2013 ◽  
Vol 58 (6) ◽  
pp. 143-150 ◽  
Author(s):  
A. Kabansky ◽  
S. S. H. Tan ◽  
E. A. Hudson ◽  
G. Delgadino ◽  
L. Gancs ◽  
...  
Keyword(s):  
Hard Mask ◽  
Dual Damascene ◽  
Damascene Process ◽  
Defect Control ◽  
Tin Metal ◽  
Low K

Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

2002 ◽  
Vol 716 ◽  
Author(s):  
C. L. Gan ◽  
C. V. Thompson ◽  
K. L. Pey ◽  
W. K. Choi ◽  
F. Wei ◽  
...  
Keyword(s):  
Stress Conditions ◽  
Experimental Characterization ◽  
Contact Lines ◽  
Tree Structures ◽  
Similar Test ◽  
Dual Damascene ◽  
Copper Interconnect ◽  
Test Conditions

AbstractElectromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Inorganic Si-O-C Antireflection Coating at 193 nm for Cu Dual Damascene Process

2003 ◽  
Vol 150 (1) ◽  
pp. G58 ◽  
Author(s):  
Sang-Yun Lee ◽  
Yong-Bae Kim ◽  
Jeong Soo Byun
Keyword(s):  
Antireflection Coating ◽  
Dual Damascene ◽  
Damascene Process ◽  
193 Nm
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