Plasma-damage optimization of the liner-removal process for 300 mm 0.13 μm copper dual-damascene BEOL manufacturing

2004 ◽  
Author(s):  
Shu-Huei Sun ◽  
Shih-Ming Chen ◽  
Joseph Weng-Liang Fang ◽  
Ching-Yu Huang ◽  
Tsai-Chun Li ◽  
...  
Keyword(s):  
Plasma Damage ◽  
Removal Process ◽  
Dual Damascene

Resist removal process in dual damascene structure integrating Cu and SiLK® for 0.18 μm technology

2000 ◽  
Vol 53 (1-4) ◽  
pp. 381-384 ◽  
Author(s):  
D. Louis ◽  
C. Arvet ◽  
E. Lajoinie ◽  
C. Peyne ◽  
S. Lee ◽  
...  
Keyword(s):  
Removal Process ◽  
Dual Damascene

Experimental Characterization of the Reliability of 3-Terminal Dual-Damascene Copper Interconnect Trees

2002 ◽  
Vol 716 ◽  
Author(s):  
C. L. Gan ◽  
C. V. Thompson ◽  
K. L. Pey ◽  
W. K. Choi ◽  
F. Wei ◽  
...  
Keyword(s):  
Stress Conditions ◽  
Experimental Characterization ◽  
Contact Lines ◽  
Tree Structures ◽  
Similar Test ◽  
Dual Damascene ◽  
Copper Interconnect ◽  
Test Conditions

AbstractElectromigration experiments have been carried out on simple Cu dual-damascene interconnect tree structures consisting of straight via-to-via (or contact-to-contact) lines with an extra via in the middle of the line. As with Al-based interconnects, the reliability of a segment in this tree strongly depends on the stress conditions of the connected segment. Beyond this, there are important differences in the results obtained under similar test conditions for Al-based and Cu-based interconnect trees. These differences are thought to be associated with variations in the architectural schemes of the two metallizations. The absence of a conducting electromigrationresistant overlayer in Cu technology, and the possibility of liner rupture at stressed vias lead to significant differences in tree reliabilities in Cu compared to Al.

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

Impact of Metal Pad Etch-Induced Plasma Damage on Dynamic Retention Time Degradation during High Temperature Stress in High Density DRAM Technology

2005 ◽  
Author(s):  
D-J Kim ◽  
I-G Kim ◽  
J-Y Noh ◽  
H-J Lee ◽  
S-H Park ◽  
...  
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
Retention Time ◽  
High Temperature Stress ◽  
High Density ◽  
Cell Junction ◽  
Antenna Effect ◽  
Plasma Damage ◽  
Root Cause ◽  
Wafer Processing

Abstract As DRAM technology extends into 12-inch diameter wafer processing, plasma-induced wafer charging is a serious problem in DRAM volume manufacture. There are currently no comprehensive reports on the potential impact of plasma damage on high density DRAM reliability. In this paper, the possible effects of floating potential at the source/drain junction of cell transistor during high-field charge injection are reported, and regarded as high-priority issues to further understand charging damage during the metal pad etching. The degradation of block edge dynamic retention time during high temperature stress, not consistent with typical reliability degradation model, is analyzed. Additionally, in order to meet the satisfactory reliability level in volume manufacture of high density DRAM technology, the paper provides the guidelines with respect to plasma damage. Unlike conventional model as gate antenna effect, the cell junction damage by the exposure of dummy BL pad to plasma, was revealed as root cause.

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