(Invited) Challenges for Ion Implantation in Power Device Processing

2017 ◽  
Vol 77 (5) ◽  
pp. 31-42 ◽  
Author(s):  
Werner Schustereder
Keyword(s):  
Ion Implantation ◽  
Power Device ◽  
Device Processing

High Temperature Ion Implantation and Activation Annealing Technologies for Mass Production of SiC Power Devices

2012 ◽  
Vol 717-720 ◽  
pp. 821-824 ◽  
Author(s):  
Kazuo Tezuka ◽  
Tatsurou Tsuyuki ◽  
Saburou Shimizu ◽  
Shinichi Nakamata ◽  
Takashi Tsuji ◽  
...  
Keyword(s):  
High Temperature ◽  
Ion Implantation ◽  
Mass Production ◽  
Production Line ◽  
Power Device ◽  
Power Devices ◽  
Key Technologies ◽  
Process Line ◽  
Activation Annealing

In this paper, we demonstrate the fabrication of SBD utilizing SiC process line specially designed for mass production of SiC power device. In SiC power device process, ion implantation and activation annealing are key technologies. Details of ion implantation system and activation annealing system designed for SiC power device production are shown. Further, device characteristics of SBD fabricated using this production line is also shown briefly.

The evolution of the ion implantation damage in device processing

2008 ◽  
Vol 19 (S1) ◽  
pp. 182-188 ◽  
Author(s):  
M. L. Polignano ◽  
I. Mica ◽  
V. Bontempo ◽  
F. Cazzaniga ◽  
M. Mariani ◽  
...  
Keyword(s):  
Ion Implantation ◽  
Implantation Damage ◽  
Device Processing

Characterization of Ultrathin Strained-Si Channel Layers of n-MOSFETs Using Transmission Electron Microscopy

2005 ◽  
Vol 864 ◽  
Author(s):  
Dalaver H. Anjum ◽  
Jian Li ◽  
Guangrui Xia ◽  
Judy L. Hoyt ◽  
Robert Hull
Keyword(s):  
Ion Implantation ◽  
Carrier Transport ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Threshold Region ◽  
Strained Si ◽  
Transmission Electron ◽  
Device Processing ◽  
Convergent Beam

AbstractStrained-Si based Field Effect Transistors (FETs) have enabled improvement of carrier transport in Metal Oxide Semiconductor (MOS)-based devices, both in the ON state of the device and in the sub-threshold region. This leads to devices with higher ratios of on-to-off current, improvements in the device sub-threshold slope, lower voltage operation, and carrier mobility enhancement. However, in order to understand the fundamental physics of these devices, it is important to address the stress conditions of the strained-Si channel layers after device processing, particularly after the ion-implantation process. In this work, we have studied Si+ self ion-implantation and thermally annealed strained-Si channel layers in n-MOSFETs. It has been observed that the density of defects in the strained-Si layer depends upon implant dose as well as thermal treatment. Using energy dispersive spectroscopy (EDS) spectra, it is found that Ge is present in the strained Si layer when analyzed after Si+ implantation and rapid thermal annealing. The presence of Ge in the strained Si channel layer causes relaxation of strain. This is verified by Convergent Beam Electron Diffraction (CBED) by measuring the lattice constant of the strained channel. It is concluded that electron mobility enhancements can be degraded in n- MOSFETs due to presence of both Ge up-diffusion and defects.

Ion implantation technology in SiC for power device applications

2014 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
Koutaro Kawahara ◽  
Hiroki Niwa ◽  
Naoki Kaji ◽  
Jun Suda
Keyword(s):  
Ion Implantation ◽  
Power Device ◽  
Device Applications

Electronically Enhanced Reaction of Process-Induced Defects in GaAs

1998 ◽  
Vol 510 ◽  
Author(s):  
K. Wada ◽  
H. Nakanishi ◽  
K. Yamada ◽  
L.C. Kimerling
Keyword(s):  
Ion Implantation ◽  
Plasma Etching ◽  
Reverse Bias ◽  
Electronic Excitation ◽  
Forward Bias ◽  
Structural Instability ◽  
Active Centers ◽  
Device Processing ◽  
Induced Defects ◽  
Defect Reaction

AbstractThe present paper reviews current understanding on enhanced reactions of process-induced defects in GaAs under electronic excitation. Device processing to be employed for point defect generation is Be ion implantation and Ar plasma etching. It is shown that reduction of electronic active centers is clearly enhanced by annealing under forward bias application and by annealing under reverse bias application at temperature as low as 200°C. The enhancement mechanisms are discussed in terms of recombination-enhanced defect reaction and structural instability induced by charge state effect.

Sign in / Sign up

Export Citation Format

Share Document